An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

An array substrate includes: a substrate; a black light-shading layer disposed on the substrate; a first metal layer correspondingly disposed on the black light-shading layer and thereby the black light-shading layer being located between the substrate and the first metal layer; an active material layer disposed on the first metal layer; a second metal layer disposed on the active material layer; a passivation layer disposed on the second metal layer and with a contact hole; a color filter layer disposed on the passivation layer; and a pixel electrode layer disposed on the color filter layer and connected to the second metal layer through the contact hole. Moreover, a liquid crystal display panel and a manufacturing method of an array substrate also are provided.

Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

An array substrate, a method of manufacturing thereof, and a display panel are provided. In the array substrate, a lesser thickness of an active layer in a GOA area achieves improved response time of thin film transistor in the GOA area, and a greater thickness of the active layer in a display area reduces diffusion of photons in the active layer, so as to decrease an influence of negative bias of thin film transistor in the display area. Additionally, different demands for characteristics of the array substrate in the display area and in the GOA area may be met, such that quality of the display panel may be improved.

A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.

An array substrate includes switching components, pixel electrodes connected to the switching components, a common electrode disposed to overlap the pixel electrodes via an insulator, first lines connected to the switching components, second lines connected to the switching components and extending while crossing the first lines, first protection circuits connected to the first lines, respectively, second protection circuits connected to the second lines, respectively, a first common line connected to the first lines via the first protection circuits, and a second common line connected to the second lines via the second protection circuits. The second common line is connected to the first common line directly or indirectly and not being connected to the common electrode.

To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

A method for manufacturing a ray detector array substrate is provided, comprising: forming a thin film transistor, a first data line and a receiving electrode on a base substrate; forming a first passivation layer on the base substrate; forming a first via hole and a second via hole in regions of the first passivation layer corresponding to the first data line and the receiving electrode, respectively; forming a photoelectric conversion layer covering the first passivation layer on the base substrate, the first via hole and the second via hole being filled with a material of the photoelectric conversion layer; etching the photoelectric conversion layer to retain a first portion of the photoelectric conversion layer inside the first via hole, and a second portion of the photoelectric conversion layer above and corresponding to the second via hole.