A load, a transistor which controls a current value supplied to the load, a capacitor, a power supply line, and first to third switches are provided. After a threshold voltage of the transistor is held by the capacitor, a potential in accordance with a video signal is inputted and a voltage that is the sum of the threshold voltage and the potential is held. Accordingly, variation in current value caused by variation in threshold voltage of the transistor can be suppressed. Therefore, a desired current can be supplied to a load such as a light emitting element. In addition, a display device with a high duty ratio can be provided by changing a potential of the power supply line.

The present application relates to an active switch, a manufacturing method thereof and a display device. The manufacturing method of the active switch includes: sequentially forming a gate electrode, a gate insulating layer, an active layer, a semiconductor composite layer and a source electrode and a drain electrode on a substrate. The semiconductor composite layer includes a first N-type heavily doped amorphous silicon layer, a first N-type lightly doped amorphous silicon layer, a second N-type heavily doped amorphous silicon layer and a second N-type lightly doped amorphous silicon layer which are sequentially stacked, where the ion doping concentration of the first N-type heavily doped amorphous silicon layer is lower than that of the second N-type heavily doped amorphous silicon layer, and the ion doping concentration of the first N-type lightly doped amorphous silicon layer is higher than that of the second N-type lightly doped amorphous silicon layer.

A display device includes an array substrate, a second substrate and a black matrix. The array substrate includes a first substrate, at least one electrostatic protecting component and a shielding layer. The first substrate has a display region and a peripheral region located outside the display region. The electrostatic protecting component is disposed on the first substrate in the peripheral region, and the electrostatic protecting component includes a semiconductor layer. The shielding layer includes an insulating material, and the shielding layer is disposed on the first substrate in the peripheral region, wherein the shielding layer overlaps the semiconductor layer. The second substrate is opposite to the first substrate. The black matrix is disposed between the second substrate and the first substrate. The shielding layer is disposed between the black matrix and the first substrate.

A driving substrate is provided. The driving substrate includes a substrate and a thin film transistor disposed on the substrate. The thin film transistor is divided into at least two active blocks. Two adjacent ones of the at least two active blocks are separated from each other by a first gap, and a ratio of the first gap to an average width of the two adjacent ones of the at least two active blocks in a first direction is greater than or equal to 0.1 and less than 0.5.

A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.

A method for manufacturing an array substrate, including: forming a plurality of first metal layer patterns on a base substrate which are independent from each other, each of the plurality of first metal layer patterns including an end at a non-display region of the array substrate; forming an insulating layer on the plurality of first metal layer patterns; and forming a semiconductor pattern on the insulating layer, a portion of semiconductor pattern is disposed directly opposite to the end of the first metal layer patterns.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

A display device includes a first support plate and a pixel region over the first support plate. A thin film transistor (TFT) structure is disposed over the first support plate and associated with the pixel region. The TFT structure includes a first metal layer over the first support plate. The first metal layer includes a gate. A silicon layer is disposed over the gate. A second metal layer is disposed over the silicon layer. The second metal layer includes a source and a drain covering a first portion of the silicon layer. An amorphous silicon layer is disposed over at least a portion of the second metal layer and a second portion of the silicon layer.

Embodiments of the present invention relate to a thin film transistor array panel and a display device including the same. An exemplary embodiment of the present invention provides a thin film transistor array panel and a display device including the same, including: an insulation substrate including an upper surface and a lower surface; a light blocking member disposed on or facing the upper surface of the insulation substrate and defining a plurality of openings; and a thin film transistor disposed on the upper surface of the insulation substrate. The insulation substrate may include a plurality of recesses formed in the opening in the lower surface of the insulation substrate, each recess positioned to correspond to one of the openings.

An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate. A signal transmission line, first and second insulator layers, a pixel electrode layer and a common electrode layer are disposed on the substrate; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line; and wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer, and the signal transmission line is electrically connected with the common electrode layer. A parasitic capacitance between the signal transmission line and the common electrode layer is reduced in the array substrate.