A display substrate includes a base substrate comprising a plurality of sub-pixels, a first switching element disposed on the base substrate and electrically connected to a gate line extending in a first direction and a data line extending in a second direction crossing the first direction, a color filter layer disposed on the switching element and comprising a red color filter, a green color filter, a blue color filter and a white color filter alternately disposed on the plurality of sub-pixels, respectively, a column spacer disposed on the color filter and comprising the same material as that of the white color filter, an insulation layer disposed on the color filter and the column spacer and a pixel electrode disposed on the insulation layer.

The present disclosure provides a TFT array substrate and a manufacturing method thereof. For the manufacturing method, a source electrode and a drain electrode are formed at first, and then edges of the source electrode and the drain electrode are used as masks to pattern a semiconductor layer to form an amorphous silicon island, which makes edges of the amorphous silicon island flush with the edges of the source electrode and the drain electrode, and completely removes the exposed semiconductor layer outside a metal layer, thereby decreasing photoelectric sensitivity of a TFT device, decreasing a size of the TFT device, and being beneficial for saving layouts and simplifying processes.

The present invention provides a thin-film transistor (TFT) array substrate and a manufacturing method thereof. The manufacturing method uses a four-mask process that uses an etch-stop layer on a semiconductor layer as a mask to perform alignment and etching to form a pattern of an amorphous silicon island. Tail fibers exposed outside of a source and a drain are removed, photoelectric sensitivity of a TFT device can be effectively reduced, and size of the TFT device is reduced, which can simplify processes, save layout space, and effectively increase display quality of large-size and high-resolution liquid crystal panels under high backlight intensity.

The present disclosure relates to an array substrate and a method for manufacturing the array substrate. The array substrate includes a substrate having a display region and a peripheral region surrounding the display region, the display region including sub-pixels arranged in an array, and a plurality of thin film transistors located on the substrate, including a plurality of first thin film transistors located within the peripheral region and a second thin film transistor located within each sub-pixel of the display region, wherein there is a first distance in a row and/or column direction between first active layers of the first thin film transistors and second active layers of nearest neighbor second thin film transistors, and there is a second distance in a row and/or column direction between adjacent second active layers, wherein the first distance is substantially equal to the second distance.

The present application discloses an array substrate, a display panel and a display device. The array substrate comprises: a plurality of data lines and a plurality of gate lines, a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines, each pixel unit comprising a first pixel electrode, a second pixel electrode, and at least three thin film transistors, the pixel unit further comprising: a charge-discharge element, the charge-discharge element and a third thin film transistor in the at least three thin film transistors charging and discharging the pixel unit such that the pixel unit forms a first voltage region and a second voltage region with different voltages.

A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.

Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.

The present application relates to an active switch, a manufacturing method thereof and a display device. The manufacturing method of the active switch includes: sequentially forming a gate electrode, a gate insulating layer, an active layer, a semiconductor composite layer and a source electrode and a drain electrode on a substrate. The semiconductor composite layer includes a first N-type heavily doped amorphous silicon layer, a first N-type lightly doped amorphous silicon layer, a second N-type heavily doped amorphous silicon layer and a second N-type lightly doped amorphous silicon layer which are sequentially stacked, where the ion doping concentration of the first N-type heavily doped amorphous silicon layer is lower than that of the second N-type heavily doped amorphous silicon layer, and the ion doping concentration of the first N-type lightly doped amorphous silicon layer is higher than that of the second N-type lightly doped amorphous silicon layer.

A semiconductor device capable of measuring a minute current is provided. The semiconductor device includes an operational amplifier and a diode element. An inverting input terminal of the operational amplifier and an input terminal of the diode element are electrically connected to a first terminal to which current is input, and an output terminal of the operational amplifier and an output terminal of the diode element are electrically connected to a second terminal from which voltage is output. A diode-connected transistor that includes a metal oxide in a channel formation region is used as the diode element. Since the off-state current of the transistor is extremely low, a minute current can flow between the first terminal and the second terminal. Thus, when voltage is output from the second terminal, a minute current that flows through the first terminal can be estimated from the voltage.

The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a dual-gate transistor and a memory cell. The memory cell is adjacent to the dual-gate transistor, wherein the memory cell and the dual-gate transistor share a common electrode.