This disclosure provides an array substrate and a method of manufacturing the same. The method includes: forming a switch element; etching on an extension of a gate insulation layer to obtain a second amorphous silicon layer, a second N-type amorphous silicon layer and a light sensing metal at the same time to form a photosensor; forming a light sensing layer and a passivation layer on a source metal, a drain metal, and the light sensing metal; and forming a first light sensing layer and a first passivation layer on the source metal and the drain metal, and forming a second light sensing layer and a second passivation layer on the light sensing metal by using a second mask.

A thin film transistor, an array substrate, a display device and a method for manufacturing a thin film transistor are provided. The thin film transistor is formed on a base substrate and includes a source; a drain; and a semiconductor active layer having an amorphous silicon layer and one polysilicon portion or a plurality of polysilicon portions, the amorphous silicon layer being contacted with the one polysilicon portion or the plurality of polysilicon portions. The method includes a process of forming a source, a drain, and a semiconductor active layer: wherein forming a semiconductor active layer comprises: forming a first amorphous silicon thin film on a base substrate; and performing a crystallization treatment to the first amorphous silicon thin film to convert a part of the amorphous silicon in the first amorphous silicon thin film into polysilicon, such that a semiconductor active layer comprising one polysilicon portion or a plurality of polysilicon portions are formed.

The present disclosure provides a TFT array substrate and a manufacturing method thereof. For the manufacturing method, a source electrode and a drain electrode are formed at first, and then edges of the source electrode and the drain electrode are used as masks to pattern a semiconductor layer to form an amorphous silicon island, which makes edges of the amorphous silicon island flush with the edges of the source electrode and the drain electrode, and completely removes the exposed semiconductor layer outside a metal layer, thereby decreasing photoelectric sensitivity of a TFT device, decreasing a size of the TFT device, and being beneficial for saving layouts and simplifying processes.

A display panel, a manufacturing method thereof and a display device are provided. The display panel includes a substrate and a plurality of active switches disposed on the substrate. The active switch includes a gate layer disposed on a bottom portion. The gate layer is wound with an insulation medium layer, and the insulation medium layer includes a light-obstructing layer disposed on a side portion of the gate layer.

A thin film transistor includes an active layer, a source electrode and a drain electrode. The active layer includes a conductive region and the conductive region is between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode.

The present disclosure discloses a manufacturing method for an array substrate and an array substrate. The method includes: forming a gate electrode, a gate insulating layer, a semiconductor layer, a source drain electrode layer and a photoresist layer on a substrate; patterning the photoresist layer to form a patterned photoresist layer; performing at least one wet etching on the source drain electrode layer and performing at least one dry etching on the semiconductor layer; performing an ashing processing between the steps of the wet etching and the dry etching. A ratio of a lateral etching rate to a longitudinal etching rate in the at least one ashing processing ranges from 1:0.9 to 1:1.5.

A TFT substrate includes a transmission and/or reception region including a plurality of antenna unit regions, and a non-transmission and/or reception region located in a region other than the transmission and/or reception region. Each of the antenna unit regions U includes a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate includes a gate metal layer including a gate electrode of the TFT, a gate insulating layer, a source metal layer including a source electrode of the TFT and the drain electrode, a first insulating layer, a patch metal layer including the patch electrode, a second insulating layer, and an upper conductive layer. The upper conductive layer includes a patch drain connection section electrically connected to the patch electrode and the drain electrode.

In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured.