A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

A liquid crystal cell according to the present invention includes: a TFT substrate including a first dielectric substrate, TFTs supported on the first dielectric substrate, and patch electrodes electrically connected to the TFTs; a slot substrate including a second dielectric substrate and a slot electrode including slots supported on the second dielectric substrate; a liquid crystal layer interposed between the TFT substrate and the slot substrate which are arranged in a form in which the patch electrode and the slot electrode face each other; antenna units each including one of the patch electrodes and the slot electrode including at least one of the slots arranged corresponding to the one of the patch electrodes; and alignment films formed on surfaces of both of the TFT substrate and the slot substrate facing the liquid crystal layer, made of a polyimide-based resin, and having a relative dielectric constant of 3.8 or more.

A display device includes a substrate, a plurality of pixels above the substrate, each of the pixels including a light emitting element, a display region including the plurality of pixels, a thin film transistor which each of the plurality of pixels includes, a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element, a sealing film including a second inorganic insulating material and covering the light emitting element, and at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film, wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.

The present disclosure discloses a manufacturing method of an array substrate, an array substrate, a display panel and a display device. The manufacturing method includes: forming a metal layer on a base substrate; forming a protective layer on the side, away from the base substrate, of the metal layer, wherein the protective layer is configured to protect the metal layer; forming photoresist on the side, away from the base substrate, of the protective layer; and processing the base substrate, on which the metal layer, the protective layer and the photoresist are formed, by means of a photoetching process to obtain a metal pattern.

To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

A thin film transistor according to one embodiment comprises a gate electrode; a semiconductor layer being formed using amorphous silicon and comprising a region overlapping with the gate electrode; a gate insulating layer; and a source electrode and a drain electrode facing each other with a predetermined interval therebetween. The gate electrode comprises a first layer having a first work function; and a second layer having a second work function and being interposed between the first layer and the gate insulating layer. The semiconductor layer comprises an intrinsic region being formed with non-doped amorphous silicon; and a low concentration impurities region. The second work function is less than the first work function when n-type impurities are contained in the low concentration impurities region, while the second work function is greater than the first work function when p-type impurities are contained in the low concentration impurities region.

Provided are a thin film transistor structure, a manufacturing method thereof, and a display device. The method comprises: providing a substrate (10), and sequentially forming a gate (20), a gate insulating layer (30), an active layer (40), a doped layer (50), a source (610), a drain (620) and a channel region (70) on the substrate (10); placing the channel region (70) in a preset gas atmosphere for heating treatment; wherein, the channel region (70) is placed in a nitrogen atmosphere to heat for a first preset time, in a mixed atmosphere of nitrogen and ammonia to heat for a second preset time, in an ammonia atmosphere to heat for a third preset time; or first heating the channel region (70) for a fourth preset time, finally placing in the ammonia atmosphere to heat for a fifth preset time.

A thin film transistor includes an active layer, a source electrode and a drain electrode. The active layer includes a conductive region and the conductive region is between the source electrode and the drain electrode and is spaced apart from at least one of the source electrode and the drain electrode.

According to one embodiment, a display device includes a display panel and a drive circuit. A transistor provided in a pixel portion or a peripheral portion of the display panel includes a semiconductor layer having a first end and a second end, first and second gate electrodes overlapping the semiconductor layer, a source electrode connected to the first end, and a drain electrode connected to the second end. The first and second gate electrodes are disposed in a first layer. The source electrode and the drain electrode are disposed in a second layer. The source electrode is formed to cover at least a first channel region in planar view. The drain electrode is formed to cover at least a second channel region in planar view.

The present application discloses a thin film transistor having an active layer including a channel part, a source contact part, and a drain contact part. At least one of the source contact part and the drain contact part has a contacting edge having one or more irregularities along the contacting edge.