A display device includes: a substrate; a buffer layer on the substrate; a driving transistor on the buffer layer and including a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode; and a switching transistor on the buffer layer and spaced apart from the driving transistor, the switching transistor including a second semiconductor pattern, a second gate electrode, a second source electrode, and a second drain electrode, wherein the buffer layer includes a first buffer layer including silicon nitride and a second buffer layer including silicon oxide, only the second buffer layer is under the first semiconductor pattern of the driving transistor, and the first buffer layer and the second buffer layer are under the second semiconductor pattern of the switching transistor.

The display apparatus includes a substrate, a first active layer disposed on the substrate, a first gate layer disposed on a layer covering the first active layer, the first gate layer including a first gate electrode, a second gate layer disposed on a layer covering the first gate layer, the second gate layer including an initialization line including a first part of a second electrode; a second active layer disposed on a layer covering the second gate layer, the second active layer including a second active region overlapping the first part of the second electrode; a third gate layer disposed on a layer covering the second active layer, the third gate layer including a second part of the second electrode overlapping the second active region; and a first source/drain layer disposed on a layer covering the third gate layer, the first source/drain layer including a first connection line.

A thin film transistor (TFT) is provided which is capable of reducing leakage currents in a polycrystalline silicon TFT without causing an increase in manufacturing processes. Source/drain regions of an activated layer of the TFT to be formed in a circuit region and pixel region formed on a glass substrate of a liquid crystal display panel for a mobile phone is formed so that its boron impurity falls within a range of 2.5×10.sup.18/cm.sup.3 to 5.5×10.sup.18/cm.sup.3 and its impurity activation falls within a range of 1% to 7%.

Disclosed are a crystalline p-type semiconductor film having a plurality of crystal grains with an average grain size of submicron and including a tin-doped copper halide, and a semiconductor device, a thin film transistor, a diode, and an electronic device including the same.

Disclosed are a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), a method for fabricating the same, an array substrate, a display panel, and a display device. The LTPS TFT includes an active layer, a source, a drain, a gate, and a gate insulating layer which are arranged on a substrate. The gate insulating layer is arranged between the active layer and the gate, and a graphene oxide layer which is arranged between the active layer and the gate insulating layer. Since the graphene oxide layer is arranged between the active layer and the gate insulating layer, the interface between the active layer and the gate insulating layer of polycrystalline (P-Si) has a reduced roughness and interfacial defect density, and a pre-cleaning process is not necessary for the gate insulating layer.

An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate. A signal transmission line, first and second insulator layers, a pixel electrode layer and a common electrode layer are disposed on the substrate; wherein the signal transmission line, the first insulator layer and the second insulator layer are disposed between the common electrode layer and the pixel electrode layer, the signal transmission line is disposed on the first insulator layer, and the second insulator layer is disposed on the signal transmission line; and wherein a dielectric constant of the first insulator layer is less than or equal to a dielectric constant of the second insulator layer, and the signal transmission line is electrically connected with the common electrode layer. A parasitic capacitance between the signal transmission line and the common electrode layer is reduced in the array substrate.

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

A display panel includes: a base substrate; a circuit layer on the base substrate; and a display element layer on the circuit layer, wherein the circuit layer includes an active layer on the base substrate and containing boron and fluorine; a control electrode on the active layer; and a control electrode insulation layer between the active layer and the control electrode, wherein the active layer includes: a core layer in which a concentration of the boron is greater than a concentration of the fluorine; and a surface layer on the core layer and in which a concentration of the fluorine is greater than a concentration of the boron.

A pixel of a display device includes a light emitting element, a first transistor, a second transistor, a first capacitor, and a second capacitor. A gate electrode of the first transistor is disposed under the first insulating layer, and the gate electrode of the first transistor defines the first electrode of the first capacitor. A first conductive pattern defining a second electrode of the first capacitor and a first electrode of the second capacitor is interposed between a first insulating layer and a second insulating layer. A second conductive pattern defining a second electrode of the second capacitor is interposed between the second insulating layer and a third insulating layer. A second electrode of the second transistor is electrically connected to the first conductive pattern.

According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.