A temporary bond method and apparatus for allowing wafers, chips or chiplets. To be tested, the temporary bond method and apparatus comprising: a temporary connection apparatus having one of more knife-edged microstructures, wherein the temporary connection apparatus serves, in use, as a probe device for probing the chiplets, each chiplet including a die having one or more flat contact pads which mate with the one of more knife-edged microstructures of the temporary connection apparatus; a press apparatus for applying pressure between the one or more flat contact pads on the chiplet with the one of more knife-edged microstructures of the temporary connection apparatus thereby forming a temporary bond between the temporary connection pad with the knife-edged microstructure in contact with the one or more flat wafer pads; the press being able to apply a pressure to maintain the temporary bond connection during or prior to testing of the chiplet.

Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package.

As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.

A contact probe having a first end portion and a second end portion, a probe body extended along a longitudinal development direction between the first end portion and the second end portion is disclosed. The probe body has a pair of arms separated by a slot and extending according to the longitudinal development direction and a conductive insert extended along the longitudinal development direction, in a bending plane of the contact probe. The conductive insert is made of a first material and the contact probe is made of a second material and the first material has a lower electrical resistivity than an electrical resistivity of the second material. The conductive insert is a power transmission element of the contact probe and the arms are structural support elements of the contact probe during a deformation of the probe body.

The present disclosure provides a semiconductor testing apparatus with a connected unit, which is applied to a wafer probing testing or a final testing. The semiconductor testing apparatus comprises a semiconductor testing printed circuit board, a functional module and the connected unit. First contact points are disposed on a first surface of the semiconductor testing printed circuit board, and electrically connected to the functional module. Second contact points are disposed on a second surface of the semiconductor testing printed circuit board, and electrically connected to a functional controller. The first contact points and the second contact points have independent and non-interfering working time domains. Therefore, the present disclosure can utilize the area of the semiconductor testing printed circuit board, and can independently perform functional testing of a wafer or packaged integrated circuit devices using multiple time domains, in a multi-time domain, synchronous or asynchronous manner.

A probe head for a testing apparatus integrated on a semiconductor wafer is disclosed having a first plurality of contact probes having a first transversal diameter, a second plurality of micro contact probes having a second transversal diameter, smaller than the first transversal diameter, and a flexible membrane having conductive tracks for connecting a first plurality contact probe with a corresponding second plurality micro contact probe. The second plurality contact probes are arranged between the testing apparatus and the flexible membrane, and the second plurality micro contact probes are arranged between the flexible membrane and a semiconductor wafer. The second plurality micro contact probes are configured to abut onto contact pads of a device under test integrated in the semiconductor wafer, with each first plurality contact probe being in contact with a corresponding second plurality micro contact probe through a conductive track of the flexible membrane to connect the device under test with the testing apparatus.

A probe chip consisting of multiple probes integrated on a single substrate. The layout of the probes could be designed to match specific features on the device under test. The probes are spring-loaded to allow for reversible deformation during contacting of the device under test. The probe chip provides for detailed electrical and mechanical testing of integrated circuits (IC).

Embodiments are directed to the formation micro-scale or millimeter scale structures or methods of making such structures wherein the structures are formed from at least one sheet structural material and may include additional sheet structural materials or deposited structural materials wherein all or a portion of the patterning of the structural materials occurs via laser cutting. In some embodiments, selective deposition is used to provide a portion of the patterning. In some embodiments the structural material or structural materials are bounded from below by a sacrificial bridging material (e.g. a metal) and possibly from above by a sacrificial capping material (e.g. a metal).

Embodiments are directed to microscale and millimeter scale multi-layer structures (e.g., probe structures for making contact between two electronic components for example in semiconductor wafer, chip, and electronic component test applications). One or more layers of the structures include shell and core regions formed of different materials wherein the core regions are offset from a symmetric, longitudinally extending position.

The terminals of a device under test are temporarily electrically connected to corresponding contact pads on a load board by a series of electrically conductive pin pairs. The pin pairs are held in place by an interposer membrane that includes a top contact plate facing the device under test, a bottom contact plate facing the load board, and a vertically resilient, non-conductive member between the top and bottom contact plates. Each pin pair includes a top and bottom pin, which extend beyond the top and bottom contact plates, respectively, toward the device under test and the load board, respectively. The top and bottom pins contact each other at an interface that is inclined with respect to the membrane surface normal. When compressed longitudinally, the pins translate toward each other by sliding along the interface. The sliding is largely longitudinal, with a small and desirable lateral component determined by the inclination of the interface.