A temporary bond method and apparatus for allowing wafers, chips or chiplets. To be tested, the temporary bond method and apparatus comprising: a temporary connection apparatus having one of more knife-edged microstructures, wherein the temporary connection apparatus serves, in use, as a probe device for probing the chiplets, each chiplet including a die having one or more flat contact pads which mate with the one of more knife-edged microstructures of the temporary connection apparatus; a press apparatus for applying pressure between the one or more flat contact pads on the chiplet with the one of more knife-edged microstructures of the temporary connection apparatus thereby forming a temporary bond between the temporary connection pad with the knife-edged microstructure in contact with the one or more flat wafer pads; the press being able to apply a pressure to maintain the temporary bond connection during or prior to testing of the chiplet.

Proposed are an anodic aluminum oxide structure made of anodic aluminum oxide, a probe head having the same, and a probe card having the same. More particularly, proposed are an anodic aluminum oxide structure that has a fine size and pitch guide hole and facilitates insertion of a probe, a probe head having the same, and a probe card having the same.

Proposed are a probe head and a probe card having the same. The probe head includes: an upper guide plate having an upper guide hole; a lower guide plate having a lower guide hole; an intermediate guide plate having an intermediate guide hole, and provided between the upper guide plate and the lower guide plate; and a guide member provided at a side of the intermediate guide plate, wherein the intermediate guide plate is limited in movement by the guide member.

A probe card device and a self-aligned probe are provided. The self-aligned probe includes a fixing end portion configured to be abutted against a space transformer, a testing end portion configured to detachably abut against a device under test (DUT), a first connection portion connected to the fixing end portion, a second connection portion connected to the testing end portion, and an arced portion that connects the first connection portion and the second connection portion. The fixing end portion and the testing end portion jointly define a reference line passing there-through. The first connection portion has an aligned protrusion, and a maximum distance between the arced portion and the reference line is greater than 75 μm and is less than 150 μm.

A probe card device and a disposable adjustment film thereof are provided. The disposable adjustment film is integrally formed as a single one-piece structure, and includes a probe hole and a plurality of first slots that are parallel to each other. The disposable adjustment film defines two predetermined lines respectively extending from two opposite lateral edges thereof to the probe hole. The two predetermined lines respectively extend across the first slots. In a plane that the disposable adjustment film is located thereon, when the disposable adjustment film is applied with forces that act in opposite directions and that are parallel to any one of the first slots, the disposable adjustment film is broken into two abandoned films along the two predetermined lines.

A reduced pin count (RPC) device includes an electrical circuitry in a package with uniformly distributed leads, a subset of the leads being electrically disconnected form the circuitry. A contactor pin block with sockets corresponding to the uniformly distributed leads has the sockets corresponding to the leads with electrical connections filled with test pins suitable for contacting respective leads, and the sockets corresponding to the electrically disconnected leads voided of test pins. Dummy plugs are inserted into the voided sockets to block the sockets and prevent accidental insertions of test pins.

The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

A ceramic contains, in mass percent: Si.sub.3N.sub.4: 20.0 to 60.0%, ZrO.sub.2: 25.0 to 70.0%, and one or more oxides selected from MgO, Y.sub.2O.sub.3, CeO.sub.2, CaO, HfO.sub.2, TiO.sub.2, Al.sub.2O.sub.3, SiO.sub.2, MoO.sub.3, CrO, CoO, ZnO, Ga.sub.2O.sub.3, Ta.sub.2O.sub.5, NiO, and V.sub.2O.sub.5: 5.0 to 15.0%. The ceramic has a coefficient of thermal expansion as high as that of silicon and an excellent mechanical strength, allows fine machining with high precision, and prevents particles from being produced.

A probe card device including a probe structure is provided. Probes respectively pass through multiple through holes on at least two guide plates that are stacked and separated from each other, and each of the probes includes a main body, a contacting portion, a head portion, and a neck portion. The contacting portion is exposed under a lowermost guide plate. The head portion is exposed above an uppermost guide plate. The neck portion is connected between the main body and the head portion, and a part of the neck portion protrudes opposite thereof to form a protrusion portion. The protrusion portion and the main body form an included angle, the protrusion portion abuts against an upper surface of the uppermost guide plate, and a spacing between any two of the probes that are adjacent to each other is less than twice the thickness of the protrusion portion.

The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.