A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

A chip health monitor includes a processor configured to operate as a state machine based on instructions stored in a storage device. The state machine is configured to exercise a signal path in a chip in response to a condition and determine presence of an error in the signal path based on results from the exercise. The state machine is configured to compensate for the error by changing at least one operational parameter of the chip.

A partial discharge calibration standard apparatus may include a first and second rigid members defining respective first and second facing surfaces. An electrically insulating material may be disposed between the facing surfaces. The apparatus may further include a pressure member maintaining the rigid members together, thereby fixing the first and second facing surfaces in a substantially parallel spaced relation across the insulating material such that a partial discharge threshold magnitude for an electrical potential difference between the first and second facing surfaces is determined. The insulating material may prevent a partial discharge of an electrical potential from the first facing surface to the second facing surface below the partial discharge threshold magnitude, while allowing the electrical potential difference to be discharged from the first facing surface to the second facing surface through the insulating material when the electrical potential difference is increased to the partial discharge threshold magnitude.

The invention concerns a test program executor for an Automated Test Equipment, wherein the test program executor is configured to execute a test flow having a plurality of test suites, wherein the test program executor is configured to asynchronously execute the plurality of test suites, wherein a test suite contains a call of a function of a subsystem, wherein the function of the subsystem is related with a subsystem operation that is to be executed by the subsystem, and to signal a call of a function of a subsystem by transmitting an asynchronous request to the subsystem, the asynchronous request having a call-specific call tree hierarchy address and the call-specific operation to be executed by the subsystem, and wherein the test program executor is further configured to determine an execution order of the subsystem operations, such that the execution order of the subsystem operations depends on their call-specific call tree hierarchy addresses.

An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

Some embodiments are directed to a test apparatus for testing a device. The apparatus includes a test device having a memory for storing data processing instructions and processors configured, when the data processing instructions are executed, to execute test code in order to implement a test operation on the device being tested. The test code defines test patterns and test algorithms to be applied to instruments for testing the device being tested, and is in a first format that is independent of the test interface between the test device and the device being tested. The apparatus also includes an interface controller coupled to the device being tested and configured to convert communications generated by the test device during the execution of the test code into a second format suitable for the test interface, and to convert communications from the device being tested into the first format.

A partial discharge calibration standard apparatus may include a first and second rigid members defining respective first and second facing surfaces. An electrically insulating material may be disposed between the facing surfaces. The apparatus may further include a pressure member maintaining the rigid members together, thereby fixing the first and second facing surfaces in a substantially parallel spaced relation across the insulating material such that a partial discharge threshold magnitude for an electrical potential difference between the first and second facing surfaces is determined. The insulating material may prevent a partial discharge of an electrical potential from the first facing surface to the second facing surface below the partial discharge threshold magnitude, while allowing the electrical potential difference to be discharged from the first facing surface to the second facing surface through the insulating material when the electrical potential difference is increased to the partial discharge threshold magnitude.

A chip health monitor includes a processor configured to operate as a state machine based on instructions stored in a storage device. The state machine is configured to exercise a signal path in a chip in response to a condition and determine presence of an error in the signal path based on results from the exercise. The state machine is configured to compensate for the error by changing at least one operational parameter of the chip.

A power supply device for a test equipment, test equipment having a power supply device and a method for operating a power supply device are described. The power supply device is configured for an at least partly capacitive load and has an output voltage provider configured to generate a target voltage, which is energized by an input supply voltage provided at an input of the power supply, wherein the target voltage generates an output supply voltage at the capacitive load, when the capacitive load is connected to an output of the power supply and a supply current monitor configured to monitor supply current flowing into the input of the power supply and to temporarily reduce the target voltage generating the output supply voltage, if a current value of the supply current exceeds a first predetermined threshold.

A device for dynamic signal generation and analysis, which combines an arbitrary waveform generator AWG (3) with a digital signal analysis unit DSAU (23). The two units are interfaced by means of a synchronization unit SU (30), which enables a flexible scheme for controlling how the playback of the waveforms is started as well as synchronizing the recording of the results of the digital signal analysis unit synchronously to specific generated waveforms. The various units of the device are synchronous circuits clocked by a common system clock signal. At least one common numerically controlled oscillator NCO (40) is provided for the arbitrary waveform generator AWG (3) and the digital signal analysis unit DSAU (23).