A test board configured to test a device under test includes: a connection region including first and second connection terminals for contacting the device under test; and a first surface mount device located adjacent to the connection region, wherein the first connection terminal is configured to be electrically connected to a first voltage regulator of the device under test, wherein the second connection terminal is configured to be electrically connected to a second voltage regulator of the device under test, and wherein the first surface mount device is configured to be electrically connected to each of the first and second connection terminals.

An error rate measuring apparatus includes a data transmission unit that transmits a test signal of a known pattern and a parameter value defined by a communication standard to a device under test, and a bit error measurement unit that measures a bit error of a signal transmitted from the device under test. The data transmission unit sequentially changes the parameter value and transmits the parameter value to the device under test. The bit error measurement unit measures a bit error of a signal transmitted from the device under test corresponding to the parameter value. The error rate measuring apparatus further includes a discrimination unit that discriminates a parameter value at which the number of bit errors is the least in a measurement result of the bit error measurement unit, as an optimum value of emphasis of an output waveform of the device under test.

Embodiments of the present invention provide an automated test equipment (a “tester”) for testing a device under test, including a bidirectional dedicated real-time handler interface. Some embodiments include an interface having a trigger function, a fixed endpoint interface, an interface arranged on a test head, and/or a number of lines/communication channels adapted to a specific communication task, without separate signal lines, for example. The bidirectional dedicated real-time handler interface can be used to transmit thermal control signals, and the transmitted signals can be test site specific. The real-time signaling advantageously improves testing accuracy and efficiency.

A ground fault detection circuit can include a band-pass filter that can have a first node and a second node that can be coupled to an earth ground. The first node can be coupled to a local ground of an automatic test equipment (ATE) system for an electrical device that can be coupled via at least one wire to the ATE. The band-pass filter can be configured to pass and amplify a test current signal established at the first node in response to a coupling of one of a conductor of the at least one wire carrying the test current signal to the local ground, and a conductive element of the electrical device carrying the test current signal to the local ground. A fault alert signal can be provided to provide an indication of ground fault based on a comparison of the amplified test current signal.

A high-frequency coaxial attenuator includes a first coaxial cable portion that includes a first center conductor having a first length, and a first insulator of the first length formed around the first center conductor, wherein the first center conductor and the first insulator form a first diameter. A second coaxial cable portion is separated from the first coaxial cable portion by a gap. The second coaxial cable portion includes a second center conductor having a second length, and a second insulator of the second length formed around the second center conductor. A semiconductor material is deposited in the gap between the first coaxial cable portion and the second coaxial cable portion. The semiconductor material may be configured to provide an impedance of 500Ω and provides 20 dB of attenuation, and a 10:1 voltage divider based on a 50Ω input impedance of test equipment.

A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.

Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.

The present invention provides a chip test method, apparatus, device, and system. The chip test system may include: a test equipment, including n chip selection signal lines, m sets of first signal lines, and m*n sets of second signal lines; and m*n chip test sites, wherein each chip test site may be coupled to one of the n chip selection signal lines and one of the m sets of first signal lines, each of the m*n chip test sites may correspond to a unique combination of a chip selection signal line and a first signal line coupled thereto, and each chip test site may be correspondingly coupled to one of the m*n sets of second signal lines. According to an embodiment of the present invention, the limited pins of a test equipment may be used to implement individual control of multiple chips.

Controlling of drop test equipment. A predefined test script is obtained over a machine-machine interface. The test script comprises plurality of test settings for drop testing of a device-under-test, DUT. The drop test equipment is controlled to perform drop testing of the DUT according to the test settings of the test script. Test results are collected and provided to a test report.