A test and measurement system includes a test and measurement device configured to receive a signal from a device under test, and one or more processors configured to execute code that causes the one or more processors to generate a waveform from the signal, apply an equalizer to the waveform, receive an input identifying one or more measurements to be made on the waveform, select a number of unit intervals (UIs) for a known data pattern, scan the waveform for the known data patterns having a length of the number of UIs, identify the known data patterns as short pattern waveforms, apply a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and provide the values of the one or more measurements for the waveform. A method includes receiving a signal from a device under test, generating a waveform from the signal, applying an equalizer to the waveform, receiving an input identifying one or more measurements to be made on the waveform, selecting a number of unit intervals (UIs), scanning the waveform to identify short pattern waveforms having a length equal to the number of UIs, applying a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and providing the values of the one or more measurements for the waveform from the machine learning system.

A device for generating waveforms includes a machine learning system configured to associate waveforms from a device under test to parameters, a user interface configured to allow a user to provide one or more user inputs, and one or more processors configured to execute code that causes the one or more processors to receive one or more inputs through the user interface that include one or more parameters, apply the machine learning system to the received one or more parameters, produce, by the machine learning system, a waveform based on the one or more parameters, and output the produced waveform. Methods of generating waveforms are also presented.

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

An integrated circuit (IC) device and a method for communicating test data utilizes test control circuitry, and a test controller. The test controller is coupled with the test control circuitry and decodes packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry. The test controller further communicates the test data to the test control circuitry, and packetizes resulting data received from the test control circuitry. The resulting data corresponds to errors identified by a test performed based on the test pattern data.

In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.

In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.

An apparatus for performing multiple tests on a device under test (DUT) are provided. The apparatus includes at least one non-transitory computer-readable medium having stored thereon computer-executable instructions and at least one processor coupled to the at least one non-transitory computer-readable medium. The computer-executable instructions are executable by the at least one processor and cause the apparatus to perform operations of inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.

In one example case, a cross-platform system includes a first automated test platform having a first test instrument and a first glue layer interface that exposes test functions to direct testing by the first test instrument. The system further includes a second automated test platform having a second test instrument and a second glue layer interface that exposes the same test functions to direct testing by the second test instrument. In the system, the glue layers abstract the respective and different control commands used by the different, first and second test instruments. Using the glue layers, the same higher-level test code can be executed by the control computers of both the first and second automated test platforms.

The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals.

In order to expedite testing (such as silicon chip testing), a test pattern that indicates a timing, order, and frequency (e.g., speed) of signals sent during the test may be divided into different portions. Also, a frequency at which each portion of the test pattern is to be run is determined. Each portion is run at a frequency that can be supported by only that portion. As a result, the slowest portion of the test pattern only limits the frequency at which its portion is run, while other portions are run at a faster frequency. This reduces a time taken to run the test pattern in a testing environment.