Embodiments of the present application provide a time offset method and device for a test signal. When a signal source sends a test signal to a DUT on a test platform, the offset device can determine a time delay caused by impedance matching of the test signal to the DUT at the upper side of each test location, and conduct time offset for TCK signals sent by the signal source to different DUTs according to the time delay.

Provided are a clock conversion device, a test system including the same, and a method of operating the test system. The clock conversion device includes a first clock generator configured to receive a first input clock signal from test logic and generate a first clock signal of which a frequency is multiplied and a phase is locked; a clock conversion circuit configured to receive the first clock signal and generate one or more second clock signals by converting at least one clock characteristic of the first clock signal; and an output selector configured to output any one of the first clock signal and the one or more second clock signals as an output clock signal, wherein the clock conversion device is configured to provide the output clock signal to a device under test (DUT).

A test and measurement instrument includes a first data channel including a first data converter operating at a first rate, and a second data channel including a second data converter operating at a second rate that is different than the first rate. Rate controls may include a clock generation circuit. The clock generation circuit includes an intermediate frequency generator structured to generate an intermediate frequency clock from a first clock reference signal, a first frequency clock generator structured to generate a first frequency clock directly from the intermediate frequency clock, and a second frequency clock generator structured to generate a second frequency clock directly from the intermediate frequency clock. The first frequency clock may be used to control the rate of the first data channel, and the second frequency clock may be used to control the rate of the second data channel. Methods are also described.

Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.

A method can be used to test an electronic circuit. The method includes applying a test stimulus signal to the input node, collecting a sequence of N-bit digital test data at the output port. The N-bit digital test data is determined by the test stimulus signal applied to the input node. The method also includes applying N-bit to R-bit lossless compression to the N-bit digital test data to obtain R-bit compressed test data (R is less than N) and making the R-bit compressed test data available in parallel format over R output pins of the circuit.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

An exemplary system includes a photodetector configured to generate a plurality of photodetector output pulses over time as a plurality of light pulses are applied to and scattered by a target, a TPSF generation circuit configured to generate, based on the photodetector output pulses, a TPSF representative of a light pulse response of the target, and a control circuit configured to direct the TPSF generation circuit to selectively operate in different resolution modes.

A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.