A test and measurement system includes a test and measurement device configured to receive a signal from a device under test, and one or more processors configured to execute code that causes the one or more processors to generate a waveform from the signal, apply an equalizer to the waveform, receive an input identifying one or more measurements to be made on the waveform, select a number of unit intervals (UIs) for a known data pattern, scan the waveform for the known data patterns having a length of the number of UIs, identify the known data patterns as short pattern waveforms, apply a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and provide the values of the one or more measurements for the waveform. A method includes receiving a signal from a device under test, generating a waveform from the signal, applying an equalizer to the waveform, receiving an input identifying one or more measurements to be made on the waveform, selecting a number of unit intervals (UIs), scanning the waveform to identify short pattern waveforms having a length equal to the number of UIs, applying a machine learning system to the short pattern waveforms to obtain a value for the one or more measurements, and providing the values of the one or more measurements for the waveform from the machine learning system.

A wafer test system includes a probe apparatus, a data server, an automation subsystem, and a probe mark assessment subsystem. The probe apparatus includes a probe card, a tester, and a camera. The probe card includes probe pins for contacting test pads in the wafer, and the camera captures an image of the test pads. The automation subsystem obtains an image specification from the probe apparatus and triggers an automated assessment of a probe mark in the image of the test pads. The probe mark assessment subsystem performs the automated assessment of the probe mark in the image of the test pads. The probe mark assessment subsystem performs an image-processing operation to obtain a probe mark assessment result, and the automation subsystem stops the probe apparatus if the probe mark assessment result indicates a probe test failure.

A testing system for monitoring a machine under test is disclosed and includes one or more high frequency sensors configured to generate a sensor signal that is representative of an operating parameter of the machine. The high frequency sensors have a required high frequency sampling rate. The testing system also includes a notification device configured to generate a notification indicating the operating parameter monitored by the high frequency sensors has exceeded a predefined threshold value and a data acquisition control module configured to monitor the high frequency sensors at a first sampling rate. The testing system also includes a monitoring control module in electronic communication with the notification device. The monitoring control module is configured to monitor the high frequency sensors at a second sampling rate that is greater than the first sampling rate and at least equal to the required high frequency sampling rate.

A test and measurement system includes a clock recovery circuit configured to receive a signal from a device under test and to produce a pattern trigger signal, a flash array digitizer having an array of counters having rows and columns configured to store a waveform image representing the signal received from the device under test, a row selection circuit configured to select a row in the array of counters, and a ring counter circuit configured to receive a clock signal, select a column in the array of counters, produce end of row signals, and produce a fill complete signal upon all of the columns having been swept, the fill complete signal indicating completion of the waveform image, an equivalent time sweep logic circuit configured to receive the pattern trigger signal and the end of row signals from the ring counter and to produce the clock signal with a delay to increment a clock delay to the ring counter until the fill complete signal is received, and a machine learning system configured to receive the waveform image and provide operating parameters for the device under test. A test and measurement system includes a flash array digitizer having an array of counters having rows and columns configured to store a waveform image representing a signal received from a device under test, a row selection circuit configured to select a row in the array of counters, a column selection circuit configured to select a column in the array of counters, a sample clock connected to the row selection circuit and the column selection circuit, and a machine learning system configured to receive the waveform image from the flash array digitizer and provide operating parameters for the device under test.

Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.

A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.

In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed.

Aspects of present disclosure relate to an integrated circuit chip (chip), a method and a computer program product of testing the chip. The method of testing the chip may include: partitioning the chip into various partitions, loading built-in self-test (BIST) test instructions into BIST engine and initializing a current partition counter, performing BIST test on current partition, transmitting test results of the current partition of the chip to an external test data storage, checking whether current partition is the last partition, incrementing current partition counter, and returning to performing BIST on a next partition when current partition is not the last partition, and exiting BIST test when current partition is the last partition. The test results may be stored in one or more inactive storage elements of the chip. The number of partitions may include: one partition, a predetermined number of partitions, and a variable number of partitions.

According to some aspects, a system and method for processing messages in a plurality of successive cycles is provided. One such system may include a plurality of first circuits, each first circuit configured to output a message, the plurality of first circuits configured to operate synchronously, a first plurality of buffers, each buffer associated with a respective first circuit and configured to store a message output by the respective first circuit, a communication path configured to receive the plurality of messages from the buffers and to perform aggregation of the messages, thereby generating an aggregated indication, and one or more second circuits. The one or more second circuits are configured to operate synchronously and to receive the aggregated indication, wherein buffers of the first plurality of buffers are configured to store messages from respective first circuits for different times.

A measurement system is described. The measurement system includes a test-and-measurement (T&A) circuit and an error analysis circuit. The T&A circuit is configured to generate measurement data. The measurement data includes at least one of analysis data and configuration data. The analysis data is associated with an analysis of at least one input signal. The configuration data is associated with at least one of a physical measurement setup of the measurement system and measurement settings of the measurement system. The T&A circuit further is configured to generate a graphic representation of the measurement data. The error analysis circuit is configured to identify errors or anomalies associated with the measurement data based on the graphic representation. Further, a measurement method is described.