Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

A voltage generation circuit of an embodiment includes: a voltage dividing circuit configured to divide applied voltage; a bias circuit configured to generate voltage by dividing power source voltage supplied through a first input terminal; and a power source switching control circuit configured to perform first processing of preventing voltage supply from a power source line to the voltage dividing circuit, connecting the power source line to a first output terminal, and connecting a ground to a second output terminal, second processing of connecting the power source line and the ground to the voltage dividing circuit, and third processing of obtaining voltage through the voltage dividing circuit by supplying voltage generated by the bias circuit to the first output terminal and supplying the voltage generated by the bias circuit to the voltage dividing circuit.

A voltage generation circuit of an embodiment includes: a voltage dividing circuit configured to divide applied voltage; a bias circuit configured to generate voltage by dividing power source voltage supplied through a first input terminal; and a power source switching control circuit configured to perform first processing of preventing voltage supply from a power source line to the voltage dividing circuit, connecting the power source line to a first output terminal, and connecting a ground to a second output terminal, second processing of connecting the power source line and the ground to the voltage dividing circuit, and third processing of obtaining voltage through the voltage dividing circuit by supplying voltage generated by the bias circuit to the first output terminal and supplying the voltage generated by the bias circuit to the voltage dividing circuit.

Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

A supply voltage sensitivity of an output current of a bias current generator circuit is reduced. The bias current generator includes a plurality of transistors and a plurality of resistors coupled to the plurality of transistors. The supply voltage sensitivity of the output current of the bias current generator circuit is reduced by applying a second bias current generated by the bias current generator circuit to a first bias current generated by the bias current generator circuit.

A supply voltage sensitivity of an output current of a bias current generator circuit is reduced. The bias current generator includes a plurality of transistors and a plurality of resistors coupled to the plurality of transistors. The supply voltage sensitivity of the output current of the bias current generator circuit is reduced by applying a second bias current generated by the bias current generator circuit to a first bias current generated by the bias current generator circuit.

An image sensing device and an operating method thereof. The image sensing device includes a ramp signal generation circuit suitable for generating a ramp signal which corresponds to an analog gain, based on a main bias voltage, a cascode bias voltage and a plurality of ramp code signals, a bias voltage generation circuit suitable for generating the main bias voltage and the cascode bias voltage according to the analog gain, and a boost circuit suitable for boosting an output terminal of the cascode bias voltage according to the analog gain.

Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.

In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.