Patent classifications
G05F3/20
Device design for short-circuitry protection circuitry within transistors
A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.
Device design for short-circuitry protection circuitry within transistors
A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal. A semiconductor structure is between the first current terminal, the second current terminal, and the control terminal and configured such that a resistance between the first current terminal and the second current terminal is based on a control signal provided at the control terminal. Short circuit protection circuitry is coupled between the control terminal and the second current terminal. In a normal mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is greater than a voltage of the control signal. In a short circuit protection mode of operation, the short circuit protection circuitry is configured to provide a voltage drop that is less than a voltage of the control signal.
Bias current generator circuit
A bias current generator circuit includes a current path and a leakage control circuit. The current path is connected between a supply voltage and a ground level. The current path includes a transistor and a resistor. The transistor has a current channel connected in the current path. The resistor has an upper terminal and a lower terminal connected in the current path, and a well contact to allow a reverse leakage current of the resistor to flow through. The leakage control circuit is connected to the supply voltage. The leakage control circuit includes a driving transistor to provide a driving voltage to the well contact of the resistor, and to allow the reverse leakage current of the resistor to flow into the leakage control circuit.
Temperature interpolation techniques for multiple integrated circuit references
Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.
Temperature interpolation techniques for multiple integrated circuit references
Techniques for providing temperature trim codes to multiple reference circuits of an integrated circuit are provided. In an example, a string of primary latch circuits can provide a set of pre-defined temperature trim codes to a multiplexer in response to a token of a series of tokens. The multiplexer can provide two trim of the trim codes to an interpolator based on a temperature reading of the integrated circuit. The interpolator can provide an interpolated trim code and the trim code can be distributed to a reference circuit based on the token.
SEMICONDUCTOR DEVICE FOR GENERATING A REFERENCE CURRENT OR VOLTAGE IN VARIOUS TEMPERATURES
A bandgap reference circuit includes a plurality of current sources including different temperature coefficients, a first trimmer, and a mixer, The first trimmer adjusts current amounts for a plurality of currents, which are individually output from each of the plurality of current sources, to be equal to each other. The mixer adjusts an aggregate ratio and combines the plurality of currents based on the aggregate ratio.
SEMICONDUCTOR DEVICE FOR GENERATING A REFERENCE CURRENT OR VOLTAGE IN VARIOUS TEMPERATURES
A bandgap reference circuit includes a plurality of current sources including different temperature coefficients, a first trimmer, and a mixer, The first trimmer adjusts current amounts for a plurality of currents, which are individually output from each of the plurality of current sources, to be equal to each other. The mixer adjusts an aggregate ratio and combines the plurality of currents based on the aggregate ratio.
BANDGAP AMPLIFIER BIASING AND STARTUP SCHEME
Systems and circuits include an amplifier having an output; a switching circuit coupled to the output of the amplifier to provide a bias current to bias the amplifier; first current generating circuitry coupled to the switching circuit; and second current generating circuitry coupled to the output of the amplifier and to the switching circuit. In operation, the switching circuit provides the bias current, during a first time period, in response to a first signal generated by the first current generating circuitry, and provides the bias current, during a second time period, after the first time period, in response to a second signal generated by the second current generating circuitry.
System, device and method for generating a biasing current
Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.
System, device and method for generating a biasing current
Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.