In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.

Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current into the common control node in response to the current-modulating transistors injecting the programming currents into the respective phase-change memory storage elements.

Crossbar arrays with reduced disturbance and methods for programming the same are disclosed. In some implementations, an apparatus comprises: a plurality of rows; a plurality of first columns; a plurality of second columns; a plurality of devices. Each of the plurality of devices is connected among one of the plurality of rows, one of the plurality of first columns, and one of the plurality of second columns. The device further comprises a shared end on the plurality of first columns or the plurality of the second columns connecting to the plurality of the devices in the same row or column; the shared end is grounding or holds a stable voltage potential. In some implementations, one of the devices is: a RRAM, a floating date, a phase change device, an SRAM, a memristor, or a device with tunable resistance. In some implementations the stable voltage potential is a constant DC voltage.

According to one embodiment, a memory device includes a first wiring line, a second wiring line, a memory cell connected between the first and second wiring lines, including a resistance change memory element having first and second resistance states, and a two-terminal switching element connected in series to the resistance change memory element, and a voltage application circuit which applies a write voltage signal having a first polarity and setting a desired resistance state to the resistance change memory element, to the memory cell, and applies, after the write voltage signal is applied to the memory cell, a second polarity voltage signal having a magnitude that prevents the two-terminal switching element from being set to the on-state, to the memory cell.

A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.

Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

The present application provides methods for programming a circuit device with reduced disturbances. The methods may include: selecting a first target device on a target row of a plurality of rows and a target column of a plurality of columns; selecting the target row; connecting the plurality of rows other than the target row to a voltage potential with the same polarity as a programming signal; grounding the target column; preparing the programming signal on the target rows; sending a pulse signal enable an access transistor on the target column; and sending the programming signal to pass the first target device.

The present invention disclosures a RRAM cell structure, comprising a first transistor and a second transistor which are connected in parallel and commonly connected to a resistive switching device; wherein, the first transistor is set with a first gate, a first source and a first drain, a first control signal is applied to the first gate, and a first source signal is applied to the first source; the second transistor is set with a second gate, a second source and a second drain, a second control signal is applied to the second gate, and a second source signal is applied to the second source; the first drain is connected with the second drain, which are commonly connected to one terminal of the resistive switching device, and a bit signal is applied to another terminal of the resistive switching device. The present invention uses cell area of a traditional 1T1R to manufacture a 2T1R cell structure, which can take into account various operating voltage requirements of the resistive switching device simultaneously, so as to significantly improve cell performances thereof.

A circuit implementing a spiking neural network that includes a learning component that can learn from temporal correlations in the spikes regardless of correlations in the rates. In some embodiments, the learning component comprises a rate-discounting component. In some embodiments, the learning rule computes a rate-normalized covariance (normcov) matrix, detects clusters in this matrix, and sets the synaptic weights according to these clusters. In some embodiments, a synapse with a long-term plasticity rule has an efficacy that is composed by a weight and a fatiguing component. In some embodiments, A Hebbian plasticity component modifies the weight component and a short-term fatigue plasticity component modifies the fatiguing component. The fatigue component increases with increases in the presynaptic spike rate. In some embodiments, the fatigue component increases are implemented in a spike-based manner. In some embodiments, the Hebbian plasticity is a spike-timing-dependent plasticity (STDP), resulting in a fatiguing STDP (FSTDP) synapse.