The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

An indium phosphide substrate, the phosphide substrate has an angle θ on the main surface side of 0°<θ≤120° for all of the planes A, the indium phosphide substrate has edge rounds on the main surface side and a surface side opposite to the main surface; wherein a chamfered width X.sub.f from the wafer edge on the main surface side is 50 μm or more to 130 μm or less; wherein a chamfered width X.sub.b from the wafer edge on the surface side opposite to the main surface is 150 μm or more to 400 μm or less; and wherein the indium phosphide substrate has a thickness of 330 μm or moreto 700 μm or less.

A method of processing a wafer having a first surface and a second surface opposite the first surface is provided. The method includes the steps of: holding the second surface of the wafer such that the first surface thereof is exposed; processing an exposed first surface side of an outer circumferential edge portion of the wafer with a processing tool including a grinding stone made of abrasive grains bound together by a bonding material, thereby forming on the outer circumferential edge portion a slanted surface that is inclined to the first surface so as to be progressively closer to the second surface in a direction from a central area of the wafer toward an outer circumferential edge thereof; and coating the first surface of the wafer with a liquid material according to a spin coating process, thereby forming a resist film on the first surface of the wafer.

A method is used to prepare the remainder of a donor substrate, from which a layer has been removed by delamination in a plane weakened by ion implantation. The remainder comprises, on a main face, an annular step corresponding to a non-removed part of the donor substrate. The method comprises the deposition of a smoothing oxide on the main face of the remainder in order to fill the inner space defined by the annular step and to cover at least part of the annular step, as well as heat treatment for densification of the smoothing oxide. A substrate is produced by the method, and the substrate may be used in subsequent processes.

Provided is an indium phosphide substrate, a semiconductor epitaxial wafer, and a method for producing an indium phosphide substrate, which can satisfactorily suppress warpage of the back surface of the substrate. The indium phosphide substrate includes a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface, wherein the back surface has a SORI value of 2.5 μm or less, as measured with the back surface of the indium phosphide substrate facing upward.

The occurrence of breaking and chipping at the wafer peripheral edge of a bonded wafer obtained by bonding a lamination wafer on a support wafer is suppressed. A lamination wafer to be bonded to a support wafer includes a large-diameter portion made of a silicon wafer whose peripheral edge is chamfered and a small-diameter portion, whose diameter is smaller than that of the large-diameter portion, formed on the large-diameter portion concentrically and integrally with the large-diameter portion, and the small-diameter portion includes a straight body portion whose side surface is perpendicular to the wafer surface, and a neck portion whose side surface is oblique with a predetermined angle to the wafer between the straight body portion and the large-diameter portion, and the small-diameter portion is formed such that the upper face of the straight body portion is to be bonded to the support wafer.

A processing method for a wafer having a chamfered portion at a peripheral edge includes a holding step of holding the wafer by a holding table, and a chamfer removing step of rotating the holding table while causing a first cutting blade to cut into the peripheral edge of the wafer while supplying a cutting liquid from a first cutting liquid supply nozzle to cut the peripheral edge of the wafer. In the chamfer removing step, a second cutting unit is positioned at a position adjacent to the first cutting unit at such a height that a second cutting blade does not make contact with the wafer and on the side of the center of the wafer as compared to the first cutting unit, and the cutting liquid is supplied from a second cutting liquid supply nozzle.

The present disclosure relates to a semiconductor packaging method. The method includes: providing a first wafer; and performing a wafer stacking operation a plurality of times. The wafer stacking operation includes: forming a first to-be-bonded wafer in the shape of a boss, where the first to-be-bonded wafer includes a base and a protrusion from the base, and orientating the protrusion toward a second to-be-bonded wafer and bonding the protrusion to the second to-be-bonded wafer; forming a first dielectric layer on a surface of the protrusion; and performing second trimming on an edge region of the protrusion and an edge region of the second to-be-bonded wafer, so that the remainder of the second to-be-bonded wafer after the second trimming is in the shape of a boss, and using the remainder of the wafer stack after the second trimming as the first to-be-bonded wafer for next wafer stacking.

A method for preparing a semiconductor device structure is provided. The method includes forming a target layer over a semiconductor substrate, and forming an energy-sensitive layer over the target layer. The method also includes performing an energy treating process on the energy-sensitive layer to transform a portion of the energy-sensitive layer into a treated portion. An untreated portion of the energy-sensitive layer is surrounded by the treated portion. The method further includes removing the treated portion, and transferring a pattern of the untreated portion of the energy-sensitive layer to the target layer such that the semiconductor substrate is exposed.

A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 μm and less than 200 μm. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 μm and 800 μm.