A wafer producing method includes a peel-off layer forming step of forming a peel-off layer by positioning a focused spot of a laser beam having a wavelength transmittable through an ingot to a depth corresponding to a thickness of the wafer to be produced from the ingot from a first end surface of the ingot and applying the laser beam to the ingot, a first chamfered portion forming step of forming a first chamfered portion by applying, from the first end surface side to a peripheral surplus region of the wafer, a laser beam having a wavelength absorbable by the wafer, a peeling-off step of peeling off the wafer to be produced, and a second chamfered portion forming step of forming a second chamfered portion by applying, from a peel-off surface side of the wafer, the laser beam having a wavelength absorbable by the wafer.

The wafer trimming device includes a chuck table configured to hold a target wafer via suction, thereby fixing the target wafer, a notch trimmer configured to trim a notch of the target wafer, and an edge trimmer configured to trim an edge of the target wafer. The notch trimmer includes a notch trimming blade configured to rotate about a rotation axis perpendicular to a circumferential surface of the target wafer. The edge trimmer includes an edge trimming blade configured to rotate about a rotation axis parallel to the circumferential surface of the target wafer.

A laminated device wafer forming method includes a laminating step of laminating a first device wafer and a second device wafer to each other, the laminating step including a position adjusting step of imaging, by an imaging unit, a first predetermined line formed on a peripheral portion on the front surface side of the first device wafer and located outside rectangular regions corresponding to devices and a second predetermined line formed on a peripheral portion on the front surface side of the second device wafer and located outside the rectangular regions corresponding to the devices, and adjusting relative positions of the first device wafer and the second device wafer by using the first predetermined line and the second predetermined line.

Provided are a method of polishing a silicon wafer and a method of producing a silicon wafer which can reduce the formation of step-forming microdefects on a silicon wafer. The method includes: a double-side polishing step of performing polishing on front and back surfaces of a silicon wafer; a notch portion polishing step of performing polishing on a beveled portion of a notch portion of the silicon wafer after the double-side polishing step; a peripheral beveled portion polishing step of performing polishing on the beveled portion on the periphery of the silicon wafer other than the beveled portion of the notch portion after the notch portion polishing step; and a finish polishing step of performing finish polishing on the front surface of the silicon wafer after the peripheral beveled portion polishing step. The notch portion polishing step is performed in a state where the front surface is wet with water.

According to one embodiment, a semiconductor wafer is formed with a plurality of first regions each provided with a circuit element and a second region between the first regions. The semiconductor wafer includes a first structure in which a first embedding material is embedded in a first recess extending in a first direction perpendicular to a surface of a substrate. The first structure is between edges of the first regions and a third region that is cut in the second region when the first regions are separated.

A method is used to prepare the remainder of a donor substrate, from which a layer has been removed by delamination in a plane weakened by ion implantation. The remainder comprises, on a main face, an annular step corresponding to a non-removed part of the donor substrate. The method comprises the deposition of a smoothing oxide on the main face of the remainder in order to fill the inner space defined by the annular step and to cover at least part of the annular step, as well as heat treatment for densification of the smoothing oxide. A substrate is produced by the method, and the substrate may be used in subsequent processes.

The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

A method evaluates an edge shape of a silicon wafer, in which as shape parameters in a wafer cross section, when defining a radial direction reference L1, a radial direction reference L2, an intersection point P1, a height reference plane L3, h1 [μm], h2 [μm], a point Px3, a straight line Lx, an angle θx, a point Px0, δ [μm], a point Px1, and a radius Rx [μm], the edge shape of the silicon wafer is measured, values of the shape parameters h1, h2, and δ are set, the shape parameters Rx and θx are calculated in accordance with the definition based on measurement data of the edge shape, and the edge shape of the silicon wafer is determined from the calculated Rx and θx to be evaluated. Consequently, a method evaluates an edge shape of a silicon wafer capable of preventing an occurrence of trouble.

A method includes bonding a front side surface of a first wafer to a second wafer; performing a multi-trimming process on the first and second wafers from a back side surface of the first wafer, the multi-trimming process comprising: performing a first trimming step from the back side surface of the first wafer to cut through a periphery of the first wafer; performing a second trimming step on the second wafer to partially cut a periphery of the second wafer to form a first step-like structure; and performing a third trimming step on the second wafer to partially cut the periphery of the second wafer to form a second step-like structure connecting down from the first step-like structure; after performing the multi-trimming process, forming a coating material at least over the periphery of the second wafer.