A process of making sensors and sensor arrays that has the ability to manipulate of the morphology or flow of an applied drop or sample over the sensor array surface at any point in the patterning process and sensors and sensor arrays having increased sensitivity and limits of detection. In addition, said process can provided real time notification of any centerline deviation. Such production process can be adjusted in real time. Thus, large numbers of units can be made—even in millions of per day—with few if any out of specification units being produced. Such process does not require large-scale clean rooms and is easily configurable.

There is provided a film forming method including: adsorbing fluorine onto a substrate on which a region in which a nitride film is exposed and a region in which an oxide film is exposed are provided adjacent to each other by supplying a fluorine-containing gas to the substrate, and forming a stepped surface on a side surface of the oxide film by selectively etching the nitride film, among the nitride film and the oxide film, so as to cause a surface of the nitride film to be more deeply recessed than a surface of the oxide film; and after the adsorbing the fluorine onto the substrate and forming the stepped surface, selectively forming a semiconductor film on the nitride film, among the nitride film and the oxide film, by supplying a raw material gas including a semiconductor material to the substrate.

A manufacturing method for insulation layer, a manufacturing method for array substrate and an array substrate are disclosed. Wherein, the manufacturing method for insulation layer comprises steps of: depositing an insulation layer on a substrate; exposing and developing the insulation layer in order to obtain the insulation layer having an opening; light curing the insulation layer having the opening; and performing a high-temperature annealing treatment to the insulation layer having the opening after being light cured. Adopting the manufacturing method for insulation layer of the present invention, a situation of deformation at the opening of the insulation layer can be reduced.

The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.

Disclosed herein are glass-based articles having a first surface having an edge, wherein a maximum optical retardation of the first surface is at the edge and the maximum optical retardation is less than or equal to about 40 nm and wherein the optical retardation decreases from the edge toward a central region of the first surface, the central region having a boundary defined by a distance from the edge toward a center point of the first surface, wherein the distance is ½ of the shortest distance from the edge to the center point.

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

Provided is a method for forming a chalcogenide thin film, the method including forming a chalcogen element-containing film on a carrier substrate, disposing the chalcogen element-containing film on a silicon wafer, wherein the surface of the silicon wafer and the surface of the chalcogen element-containing film are in contact with each other, performing heat treatment on the silicon wafer and the chalcogen element-containing film at least one time, and removing the carrier substrate. The silicon wafer has a crystal plane of (111).

A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF.sub.2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.

The present invention provides a microstructure in which evenly distributed crystal grains line up in parallel lines extending along the surface of the film, and a no-lateral-growth region left at each of locations exposed to both ends of a grain interface, which serves as a partition between the neighboring two crystal grains. According to the present invention, there are also provided: a method for forming a polycrystalline film, such as a thin polycrystalline silicon film, a thin aluminum film, and a thin copper film, which is flat and even, in surface, electrically uniform and stable, and mechanically stable; a laser crystallization device for use in manufacture of polycrystalline films, and a semiconductor device using the polycrystalline film and having good electrical property and increased breakdown voltage.

A method of producing a reduced-defect density crystalline silicon film includes forming a first intrinsic silicon film on a substrate, forming a doped film including silicon or germanium on the first intrinsic silicon film, forming a second intrinsic silicon film on the doped film, and annealing to crystallize the doped film, the second intrinsic silicon film, and the first intrinsic silicon, wherein each film is amorphous at formation, wherein crystallization initiates within the doped film. A method of forming a thin film transistor includes forming an active layer in the crystallized second intrinsic silicon layer by doping the crystallized second intrinsic silicon layer in selected areas to form source and drain regions separated by a channel portion, forming a gate insulator layer on the crystallized second intrinsic silicon layer, and forming a gate electrode pattern over the gate insulator layer.