A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate; forming a conformal SiN, SiO.sub.xC.sub.yN.sub.z layer over side and bottom surfaces of the first trenches; filling the first trenches with SiO.sub.x; forming a first mask over portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate; removing exposed portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate, forming second trenches; forming III-V, III-V.sub.xM.sub.y, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-V.sub.xM.sub.y, or Si nanowires and intervening first trenches; removing the SiO.sub.x layer, forming third trenches; and removing the second mask.

Provided herein are tapered nanowires that comprise germanium and gallium, as well as methods of forming the same. The described nanowires may also include one or more sections of a second semiconductor material. Methods of the disclosure may include vapor-liquid-solid epitaxy with a gallium catalyst. The described methods may also include depositing a gallium seed on a surface of a substrate by charging an area of the substrate using an electron beam, and directing a gallium ion beam across the surface of the substrate.

Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire.

A vertical metal oxide semiconductor field effect transistor (MOSFET) and a method for forming a vertical MOSFET is presented. The MOSFET comprises: a top contact; a bottom contact; a nanowire (602) forming a charge transport channel between the top contact and the bottom contact; and a wrap-around gate (650) enclosing the nanowire (602) circumference, the wrap-around gate (650) having an extension spanning over a portion of the nanowire (602) in a longitudinal direction of the nanowire (602), wherein the wrap-around gate (650) comprises a gate portion (614) and a field plate portion (616) for controlling a charge transport in the charge transport channel, and wherein the field plate portion (616) is arranged at a first radial distance (636) from the center of the nanowire (602) and the gate portion (614) is arranged at a second radial distance (634) from the center of the nanowire (602); characterized in that the first radial distance (636) is larger than the second radial distance (634).

A method for forming nanostructures including introducing a hollow shell into a reactor. The hollow shell has catalyst nanoparticles exposed on its interior surface. The method also includes introducing a precursor into the reactor to grow nanostructures from the interior surface of the hollow shell from the catalyst nanoparticles.

A method for detection and monitoring a therapeutic effect of a cancer treatment drug is disclosed. The method includes steps of removing a malignant biological cell lines from a tumor; culturing the removed biological cell lines in a controlled set of conditions; seeding the cultured biological cell lines on silicon nanowire electrode arrays of an electrical cell-substrate impedance sensor (ECIS); adding a cancer treatment drug to the seeded biological cell lines to treat the seeded biological cell lines; and measuring an electrical impedance of the treated biological cell lines for detection and monitoring a therapeutic effect of the cancer treatment drug.

A nanowire includes an electrically conductive catalyst nanoparticle first portion, a semiconductor wire second portion, a first dielectric shell around the first portion, and a second dielectric shell or functionalization around the second portion. A material of the second dielectric shell or functionalization is different from a material of the first shell.

The present invention generally relates to nanoscale wires and, in particular, to nanoscale wires with heterojunctions, such as tip-localized homo- or heterojunctions. In one aspect, the nanoscale wire may include a core, an inner shell surrounding the core, and an outer shell surrounding the inner shell. The outer shell may also contact the core, e.g., at an end portion of the nanoscale wire. In some cases, such nanoscale wires may be used as electrical devices. For example a p-n junction may be created where the inner shell is electrically insulating, and the core and the outer shell are p-doped and n-doped. Other aspects of the present invention generally relate to methods of making or using such nanoscale wires, devices, or kits including such nanoscale wires, or the like.

A method of growing nanowires includes forming catalyst particles including a gold-indium alloy on portions of a semiconductor substrate that are exposed by openings of a template layer disposed on the substrate, and growing the nanowires including a compound semiconductor material, such as AlP, GaP, etc., under the catalyst particles. The substrate may be reused after removing the nanowires from the substrate.

A method of manufacturing a semiconductor structure includes providing a substrate, disposing a first semiconductive material over the substrate at a first temperature, disposing a second semiconductive material over the first semiconductive material at a second temperature, and disposing a third semiconductive material over the second semiconductive material at a third temperature, wherein a first interval between the first temperature and the second temperature is substantially same as a second interval between the second temperature and the third temperature.