H01L21/02686

METHOD OF INCREASING SENSITIVITY AND LIMITS OF DETECTION AND CONTROLLING FLUID FLOW OVER SENSOR AND SENSOR ARRAY
20230045818 · 2023-02-16 ·

A process of making sensors and sensor arrays that has the ability to manipulate of the morphology or flow of an applied drop or sample over the sensor array surface at any point in the patterning process and sensors and sensor arrays having increased sensitivity and limits of detection. In addition, said process can provided real time notification of any centerline deviation. Such production process can be adjusted in real time. Thus, large numbers of units can be made—even in millions of per day—with few if any out of specification units being produced. Such process does not require large-scale clean rooms and is easily configurable.

Laser Irradiation Apparatus, Laser Irradiation Method, and Recording Medium Recording Program to be Readable
20230011292 · 2023-01-12 ·

A laser irradiation apparatus including a laser light source includes a first detection unit and a second detection unit configured to detect luminance of a substrate irradiated with laser light from the laser light source, and a control unit configured to perform control related to laser light emitted from the laser light source, in which the control unit specifies an energy density of laser light based on luminance detected by the first detection unit, specifies reference luminance based on a specified energy density and luminance detected by the second detection unit, and changes an energy density of laser light according to the reference luminance and luminance detected by the second detection unit.

LASER SYSTEM

The laser system may include a delay circuit unit, first and second trigger-correction units, and a clock generator. The delay circuit unit may receive a trigger signal, output a first delay signal obtained by delaying the trigger signal by a first delay time, and output a second delay signal obtained by delaying the trigger signal by a second delay time. The first trigger-correction unit may receive the first delay signal and output a first switch signal obtained by delaying the first delay signal by a first correction time. The second trigger-correction unit may receive the second delay signal and output a second switch signal obtained by delaying the second delay signal by a second correction time. The clock generator may generate a clock signal that is common to the delay circuit unit and the first and second trigger-correction units.

CONTROL DEVICE OF ANNEALING DEVICE, ANNEALING DEVICE, AND ANNEALING METHOD

The disclosure provides a control device of an annealing device, which is capable of further suppressing a temperature of a surface opposite to a laser irradiation surface from rising. A beam spot of a pulsed laser beam output from a laser light source on a surface of an annealed target is shaped into a long shape in one direction by a beam shaping optical element. A movement mechanism moves the beam spot with respect to the annealed target. The control device controls the laser light source and the movement mechanism and performs annealing by performing a sweep operation of moving the beam spot in a longitudinal direction of the beam spot with respect to the annealed target while causing the pulsed laser beam to be incident on the annealed target.

Transistor and methods of forming transistors
11695071 · 2023-07-04 · ·

A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately-adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately-above the internal interface physically contact at least some of the crystal grains that are immediately-below the internal interface. All of the grain boundaries that are between immediately-adjacent of the physically-contacting crystal grains that are immediately-above and that are immediately-below the interface align relative one another. The internal interface comprises at least one of (a) and (b), where (a): conductivity-modifying dopant concentration immediately-above the internal interface is lower than immediately-below the internal interface and (b): a laterally-discontinuous insulative oxide. Other embodiments, including method, are disclosed.

Laser Irradiation Apparatus, Laser Irradiation Method, and Recording Medium Recording Program to be Readable
20230006408 · 2023-01-05 ·

A laser irradiation apparatus is a laser irradiation apparatus including a plurality of laser light sources, the laser irradiation apparatus including a control unit configured to perform control with regard to laser emitted from the plurality of laser light sources, in which the control unit acquires characteristic information of each of the plurality of laser light sources, and performs a predetermined process according to each piece of acquired characteristic information.

Method of healing an implanted layer comprising a heat treatment prior to recrystallisation by laser annealing

The invention relates to a method of healing defects related to implantation of species in a donor substrate (1) made of a semiconducting material to form therein a plane of weakness (5) in it separating a thin layer (4) from a bulk part of the donor substrate. The method comprises a superficial amorphisation of the thin layer, followed by application of a heat treatment on the superficially amorphised thin layer. The method comprises application of laser annealing to the superficially amorphised thin layer after the heat treatment, to recrystallise it in the solid phase.

Multigate device having reduced contact resistivity

An exemplary device includes a channel layer, a first epitaxial source/drain feature, and a second epitaxial source/drain feature disposed over a substrate. The channel layer is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. A metal gate is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The metal gate is disposed over and physically contacts at least two sides of the channel layer. A source/drain contact is disposed over the first epitaxial source/drain feature. A doped crystalline semiconductor layer, such as a gallium-doped crystalline germanium layer, is disposed between the first epitaxial source/drain feature and the source/drain contact. The doped crystalline semiconductor layer is disposed over and physically contacts at least two sides of the first epitaxial source/drain feature. In some embodiments, the doped crystalline semiconductor layer has a contact resistivity that is less than about 1×10.sup.−9 Ω-cm.sup.2.

Crystalline semiconductor layer formed in BEOL processes

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

Source and drain epitaxial layers

The present disclosure is directed to semiconductor structures with source/drain epitaxial stacks having a low-melting point top layer and a high-melting point bottom layer. For example, a semiconductor structure includes a gate structure disposed on a fin and a recess formed in a portion of the fin not covered by the gate structure. Further, the semiconductor structure includes a source/drain epitaxial stack disposed in the recess, where the source/drain epitaxial stack has bottom layer and a top layer with a higher activated dopant concentration than the bottom layer.