A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

A method for manufacturing an epitaxial wafer by forming a single crystal silicon layer on a wafer containing a group IV element including silicon, the method including the steps of: removing a natural oxide film on a surface of the wafer containing the group IV element including silicon in an atmosphere containing hydrogen; forming an oxygen atomic layer by oxidizing the wafer after removing the natural oxide film; and forming a single crystal silicon by epitaxial growth on the surface of the wafer after forming the oxygen atomic layer, where a planar density of oxygen in the oxygen atomic layer is set to 4×10.sup.14 atoms/cm.sup.2 or less. A method for manufacturing an epitaxial wafer having an epitaxial layer of good-quality single crystal silicon while also allowing the introduction of an oxygen atomic layer in an epitaxial layer stably and simply.

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

A vertical external-cavity surface-emitting laser (VECSEL) whose blueshift is reduced also in a high intensity range of emitted laser light is realized. A surface-emitting device for VECSEL includes a base substrate made of GaN and c-axis oriented, and an emitter structure formed of a group 13 nitride semiconductor and provided on the base substrate. The emitter structure is formed of unit deposition parts, each of which is provided on the base substrate and includes a DBR layer having a distributed Bragg reflection structure and an active layer that has a multiple quantum well structure and generates excitation emission in response to irradiation with external laser light. A c-axis orientation of each of the unit deposition parts conforms to the c-axis orientation of the base substrate located directly below the unit deposition parts. Grooves are formed between the unit deposition parts.

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

There is provided a nitride crystal substrate comprising group-III nitride crystal and containing n-type impurities, wherein an absorption coefficient α is approximately expressed by equation (1) in a wavelength range of at least 1 μm or more and 3.3 μm or less: α=n Kλ.sup.a (1) (wherein, λ(μm) is a wavelength, α(cm.sup.−1) is absorption coefficient of the nitride crystal substrate at 27° C., n (cm.sup.−3) is a free electron concentration in the nitride crystal substrate, and K and a are constants, satisfying 1.5×10.sup.−19≤K≤6.0×10.sup.−19, a=3).

The invention is a special designed pattern heterogeneous substrate, which is epitaxially deposited on a heterogeneous substrate by two step growth, and a thermal cycle annealing is added to reduce the lattice mismatch between the layers and the difference in thermal expansion coefficient, thereby obtaining a better stress. The quality of the semiconductor epitaxial layer is improved, and the present invention can easily grasp the timing of stress release when the semiconductor is grown on the heterogeneous substrate, avoid cracks in the semiconductor epitaxial layer, and form a crack free zone in the middle of the semiconductor epitaxial layer.

According to one aspect of the technique of the present disclosure, there is provided a substrate processing apparatus including: a temperature detector for detecting a temperature of a heat generator for elevating a temperature of a process chamber by generating heat; a temperature regulator for adjusting a ratio of outputting an electric power capable of being supplied to the heat generator in a unit time to reduce a difference between a temperature obtained from the temperature detector and a temperature setting value; a measurer or measuring a current flowing through a circuit containing the heat generator; and an abnormality detector for comparing a current measurement value measured by the measurer and a theoretical current value calculated based on the ratio of outputting the electric power acquired from the temperature regulator and determine that there is an abnormality when the current measurement value and the theoretical current value are different.

A semiconductor substrate (1) according to an embodiment includes: a hexagonal SiC single crystal layer (13I); an SiC epitaxial growth layer (12E) disposed on an Si plane of an SiC single crystal layer (13I); and an SiC polycrystalline growth layer (18PC) disposed on a C plane opposite to the Si plane of the SiC single crystal layer (13I). The SiC single crystal layer (13I) includes a single crystal SiC thin layer (10HE) obtained by weakening the hydrogen ion implantation layer (10HI), and a phosphorus ion implantation layer (10PI). The phosphorus ion implantation layer (10PI) is disposed between the single crystal SiC thin layer (10HE) and the SiC polycrystalline growth layer (18PC). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.

Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.