A method of plasma etching a compound semiconductor substrate forms a feature. A first plasma etch step anisotropically etches the substrate through an opening to produce a partially formed feature having an opening and a bottom surface with a peripheral region. A second plasma etch step removes a region of the mask adjacent to the opening of the partially formed feature thereby causing rounding of the edges of the substrate at the opening of the partially formed feature. A third plasma etch step anisotropically etches the bottom surface of the partially formed feature through the opening of the mask while depositing a passivation material onto the mask and the opening of the partially formed feature to reduce a dimension of the opening of the partially formed feature. A plasma etch apparatus can be used to perform the method.

Described herein are etching solutions and method of using the etching solutions suitable for etching aluminum nitride (AlN) from a semiconductor substrate during the manufacture of a semiconductor device comprising AlN and silicon material without harming the silicon material. The etching solution comprises a cationic surfactant, water, a base, and a water-miscible organic solvent.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type; forming a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type; forming a plurality of trenches within the first III-nitride layer, wherein the plurality of trenches extend to a predetermined depth; epitaxially regrowing a second III-nitride structure in the trenches, wherein the second III-nitride structure is characterized by a second conductivity type; forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions; epitaxially regrowing a III-nitride gate layer in the recess regions, wherein the III-nitride gate layer is coupled to the second III-nitride structure, and wherein the III-nitride gate layer is characterized by the second conductivity type.

A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

A manufacturing method for a semiconductor element includes providing a mask including an opening on a surface of a substrate while leaving a step difference in the mask at an upper surface region around the opening, epitaxially growing a semiconductor from the surface exposed through the opening to over the upper surface region around the opening, to produce a semiconductor element including a semiconductor layer including a first surface to which the step difference is transferred, and dry-etching the first surface of the semiconductor layer to transfer the step difference, the first surface being a contact surface with the mask before the dry etching is performed. The mask contains an element that serves as a donor or an acceptor in the semiconductor layer.

A method of selectively removing NiPt material from a microelectronic substrate, the method comprising contacting the NiPt material with an aqueous etching composition comprising: an oxidising agent; a strong acid; and a source of chloride.

In a manufacturing method of a semiconductor element of the present disclosure, a first semiconductor part (SL1) includes a protruding portion (TS) protruding toward an underlying substrate (UK), the protruding portion contains a nitride semiconductor, the protruding portion and the underlying substrate are bonded to each other, a semiconductor substrate (HK) includes a hollow portion (TK) located between the underlying substrate and the first semiconductor part, the hollow portion is in contact with a side surface of the protruding portion and communicates with the outside of the semiconductor substrate, and the protruding portion (TS) is irradiated with the laser beam (LZ) before the first semiconductor part is separated from the semiconductor substrate.