A method for forming etched features in a layer of a first material is provided. A layer of a second material is deposited over the layer of the first material. An alloy layer of the first material and the second material is formed between the layer of the first material and the layer of the second material. The layer of the first material is selectively etched with respect to the alloy layer, using the alloy layer as a hardmask.

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

Integrated circuit devices and methods of forming the same are provided. The methods may include sequentially forming an underlying mask layer and a preliminary first mask layer on a substrate, forming a first mask structure by removing a portion of the preliminary first mask layer, and then forming a preliminary second mask layer. The preliminary second mask layer may enclose the first mask structure in a plan view. The methods may also include forming a second mask structure by removing a portion of the preliminary second mask layer and forming a vertical channel region including a portion of the substrate by sequentially etching the underlying mask layer and the substrate. The second mask structure may be connected to the first mask structure, and etching the underlying mask layer may be performed using the first and the second mask structures as an etch mask.

Methods for selectively etching SiGe relative to Si are provided. Some of the methods incorporate formation of a passivation layer on a surface of the Si layer to enhance SiGe etchant selectivity and the use of interhalogen gases that preferentially etch the SiGe as opposed to the Si in the presence of the passivation layer. The methods can occur in a cyclic manner until the desired thickness of the SiGe layer is obtained.

The present invention disclosures a Tip-to-Tip pattern preparation method, comprising: providing a substrate, and sequentially forming a layer to be etched, a first hard mask layer, a second hard mask layer, a sacrificial layer, a first dielectric layer and a first photoresist layer on the substrate, forming a first patterned photoresist layer which has a first Tip-to-Tip pattern by EUV lithography, and transferring the first Tip-to-Tip pattern to the second hard mask layer by etching; then forming a second patterned photoresist layer which has a second Tip-to-Tip pattern by the EUV lithography, and transferring the second Tip-to-Tip pattern to the second hard mask layer by etching; finally, transferring the first Tip-to-Tip pattern and the second Tip-to-Tip pattern to the layer to be etched. The above method needs only performing the EUV lithography twice to form the small-sized Tip-to-Tip pattern with a period halved, that is, the EUV lithography and etching are used for reducing lithography layers and realizing to form the small-sized Tip-to-Tip pattern with the period halved.

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Provided is a kit including a curable composition for imprinting, and a composition for forming an underlayer film for imprinting, in which the composition for forming an underlayer film for imprinting contains a polymer having a polymerizable functional group, and a compound in which the lower one of a boiling point and a thermal decomposition temperature is 480° C. or higher and ΔHSP, which is a Hansen solubility parameter distance from a component with the highest content contained in the curable composition for imprinting, is 2.5 or less. Furthermore, the present invention relates to a composition for forming an underlayer film for imprinting, a pattern forming method, and a method for manufacturing a semiconductor device, which are related to the kit.