An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n.sup.+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n.sup.+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n.sup.+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

A semiconductor device includes a source/drain region, a source/drain silicide layer formed on the source/drain region, and a first contact disposed over the source/drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

A method for manufacturing a semiconductor device including a TiN film. The method comprises: supplying TiCl.sub.4 gas to a substrate; purging the TiCl.sub.4 gas; supplying NH.sub.3 gas to the substrate; purging the NH.sub.3 gas; and supplying an inhibitor that inhibits adsorption of TiCl.sub.4 or NH.sub.3 to the substrate. A plurality of cycles each including the supplying the TiCl.sub.4 gas, the purging the TiCl.sub.4 gas, the supplying the NH.sub.3 gas, and the purging the NH.sub.3 gas are performed, at least a part of the plurality of cycles includes the supplying the inhibitor, and after the supplying the inhibitor is performed, the supplying the TiCl.sub.4 gas or the supplying the NH.sub.3 gas is performed without purging the inhibitor, or, after purging the inhibitor for a shorter time than the purging the TiCl.sub.4 gas or the purging the NH.sub.3 gas, the supplying the TiCl.sub.4 gas or the supplying the NH.sub.3 gas is performed.

Methods and apparatuses for processing substrates, such as during metal silicide applications, are provided. In one or more embodiments, a method of processing a substrate includes depositing an epitaxial layer on the substrate, depositing a metal silicide seed layer on the epitaxial layer, and exposing the metal silicide seed layer to a nitridation process to produce a metal silicide nitride layer from at least a portion of the metal silicide seed layer. The method also includes depositing a metal silicide bulk layer on the metal silicide nitride layer and forming or depositing a nitride capping layer on the metal silicide bulk layer, where the nitride capping layer contains a metal nitride, a silicon nitride, a metal silicide nitride, or a combination thereof.

The present disclosure provides a semiconductor device structure with conductive contact of different widths and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate, and a first conductive contact penetrating through the dielectric layer. The first conductive contact includes a first metal filling layer and a first metal silicide structure surrounding the first metal filling layer. The semiconductor device structure also includes a second conductive contact penetrating through the dielectric layer. The second conductive contact includes a second metal filling layer and a second metal silicide structure surrounding the second metal filling layer, and a first width of the first conductive contact is different from a second width of the second conductive contact.

An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

Methods for seam-less gapfill comprising forming a flowable film by PECVD and curing the flowable film to solidify the film. The flowable film can be formed using a higher order silane and plasma. A UV cure, or other cure, can be used to solidify the flowable film.