The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.

An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (Å) and 500 angstroms.

A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

The invention relates to a method of healing defects related to implantation of species in a donor substrate (1) made of a semiconducting material to form therein a plane of weakness (5) in it separating a thin layer (4) from a bulk part of the donor substrate. The method comprises a superficial amorphisation of the thin layer, followed by application of a heat treatment on the superficially amorphised thin layer. The method comprises application of laser annealing to the superficially amorphised thin layer after the heat treatment, to recrystallise it in the solid phase.

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.

A method of fabricating a semiconductor substrate includes the following steps. A carrier substrate is provided, and a plasma treatment is performed on the surface of the carrier substrate. A polycrystalline semiconductor layer is formed on the surface of the carrier substrate. A rapid thermal treatment is then performed on the polycrystalline semiconductor layer. A buried dielectric layer is then formed on the polycrystalline semiconductor layer. Afterwards, a single crystalline semiconductor layer is formed on the buried dielectric layer.

A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 Ω.Math.cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.