A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.

A semiconductor device includes first pillar-shaped semiconductor layers, a first gate insulating film formed around the first pillar-shaped semiconductor layers, gate electrodes formed of metal and formed around the first gate insulating film, gate lines formed of metal and connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped semiconductor layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped semiconductor layers, diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, pillar-shaped insulator layers formed on the second contacts, variable-resistance films formed around upper portions of the pillar-shaped insulator layers, and lower electrodes formed around lower portions of the pillar-shaped insulator layers and connected to the variable-resistance films.

Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.

A method for forming a silicon structure. A non-limiting example of the method includes forming at least two semiconductor fins on a substrate. A polymer brush material is formed over the fins and the substrate. A block copolymer (BCP) composed of a first polymer and a second polymer which are covalently bound together is applied over the polymer brush material, such that the first polymer and second polymer self-assemble into a plurality of interleaved first microdomains and second microdomains perpendicular to and within a trench between the fins. The first microdomains are composed of the first polymer and the second microdomains are composed of the second polymer. The second microdomains can be selectively removed.

A curtain airbag device mounting structure includes: a first pillar forming a part of a front pillar and extends substantially along a vehicle height direction; a second pillar forming another part of the front pillar, the second pillar being disposed on a rear side of a vehicle relative to the first pillar at a predetermined distance from the first pillar and extending substantially along the vehicle height direction; a transparent member bridged between the first pillar and the second pillar; and a curtain airbag device including a curtain airbag stored along a roof side rail and the second pillar, the curtain airbag being configured to inflate and deploy in a curtain-like fashion over a side portion of a cabin of the vehicle in case of a collision of the vehicle.

A power semiconductor device includes a semiconductor-on-insulator island having a semiconductor region and an insulation structure, the insulation structure being formed by an oxide and separating the semiconductor region from a portion of a semiconductor body of the power semiconductor device. The insulation structure includes a sidewall that laterally confines the semiconductor region; a bottom that vertically confines the semiconductor region; and a local deepening that forms at least a part of a transition between the sidewall and the bottom, wherein the local deepening extends further along the extension direction as compared to the bottom.

A method for forming a silicon structure. A non-limiting example of the method includes forming at least two semiconductor fins on a substrate. A polymer brush material is formed over the fins and the substrate. A block copolymer (BCP) composed of a first polymer and a second polymer which are covalently bound together is applied over the polymer brush material, such that the first polymer and second polymer self-assemble into a plurality of interleaved first microdomains and second microdomains perpendicular to and within a trench between the fins. The first microdomains are composed of the first polymer and the second microdomains are composed of the second polymer. The second microdomains can be selectively removed.

An electronic device includes an isolated region surrounded by an isolation ring over a semiconductor substrate. A well of a first conductivity type is located within the isolated region. A source region and a drain region of a second conductivity type are located over the well. A local-oxidation-of-silicon (LOCOS) layer is located on the well between the source and the drain, between the source and the isolation ring, and between the drain and the isolation ring. A gate electrode located between the source and the drain on said LOCOS layer.