Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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21/00
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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H01L21/70
Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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H01L21/77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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H01L21/78
with subsequent division of the substrate into plural individual devices
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H01L21/82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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H01L21/822
the substrate being a semiconductor, using silicon technology
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H01L21/8234
MIS technology; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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H01L21/823406
Combination of charge coupled devices, i.e. CCD, or BBD
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H01L21/823406

Sensing device for sensing minor charge variations
10818785 · 2020-10-27 · ·

A charge sensing device for sensing charge variations in a charge storage area includes: a TFET having at least one sense gate; and a capacitive coupling for coupling the charge storage area with the sense gate.

Sensing Device for Sensing Minor Charge Variations
20190172937 · 2019-06-06 ·

The present invention relates to a charge sensing device for sensing charge variations in a charge storage area including: a TFET having at least one sense gate; a capacitive coupling for coupling the charge storage area with the sense gate.

Semiconductor device, memory circuit, method of manufacturing semiconductor device
10269867 · 2019-04-23 · ·

A semiconductor device of the technology includes a first diffusion section (22), a second diffusion section (21), a channel section (23), a gate section (24), and a stress application section (31, 32, or 33). In a semiconductor layer (10) having a groove (10A), the first diffusion section (22) is formed at or in the vicinity of a bottom of the groove (10A), the second diffusion section (21) is formed at an upper end of the groove (10A), and the channel section (23) is formed between the first diffusion section (22) and the second diffusion section (21). The gate section (24) is buried in the groove (10A) at a position opposing the channel section (23). The stress application section (31, 32, or 33) applies one of compressive stress and tensile stress to the channel section (23) in a normal direction to the semiconductor layer (10).

Semiconductor device having symmetric and asymmetric active fins
09929155 · 2018-03-27 · ·

A semiconductor device and a method of manufacturing the same are disclosed, which may improve the operating performance of a multi-gate transistor in a highly scaled integrated circuit device. The semiconductor device includes a first active fin unit protruding on a first region of a semiconductor substrate and extending along a first direction. The first active fin unit includes at least one first active fin having left and right profiles, which are symmetric to each other about a first center line perpendicular to a top surface of the semiconductor substrate on a cut surface perpendicular to the first direction. A second active fin unit protrudes on a second region of the semiconductor substrate and includes two second active fins, each having a left and right profiles, which are asymmetric to each other about a second center line perpendicular to the top surface of the semiconductor substrate on a cut surface.