A solid-state image sensor including photoelectric conversion parts having a vertical overflow drain structure is made usable as, for example, a distance measuring sensor with high accuracy. In the solid-state image sensor, a pixel array part is formed in a well region of a second conductive type formed at a surface part of a semiconductor substrate of a first conductive type. In the pixel array part, photoelectric conversion parts each of which converts incident light into signal charges and has the vertical overflow drain structure (VOD) are arranged in a matrix form. Substrate discharge pulse signal φSub for controlling potential of the VOD is applied to a signal terminal. An impurity induced part into which impurity of the first type is induced is formed below a connecting part in the semiconductor substrate.

Provided is an a imaging device that acquires a distance image excluding influence of background light in one frame scanning period and acquires a visible image in a separate frame from a single imaging sensor, and includes an infrared light source that emits infrared light, and a solid state imaging device including a plurality of first pixels and a plurality of second pixels, which respectively include vertical overflow drains, and are arranged in a matrix on a semiconductor substrate, the plurality of first pixels converting the infrared light into signal charges, and the plurality of second pixels converting visible light into signal charges. The solid state imaging device outputs a first signal obtained from the plurality of first pixels in an irradiation period of infrared light, and a second signal obtained from the plurality of first pixels in a non-irradiation period of infrared light, in a first frame scanning period, and outputs a third signal obtained from the plurality of first pixels and a fourth signal obtained from the plurality of second pixels, in a second frame scanning period.

A photoelectric conversion apparatus includes a plurality of units each including a charge generation region disposed in a semiconductor layer. Each of a first unit and a second unit of the plurality of units includes a charge storage region configured to store charges transferred thereto from the charge generation region, a dielectric region located above the charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the charge storage region that is located between the insulator layer and the semiconductor layer, and the first light-shielding layer having an opening located above the charge generation region. The charge generation region of the first unit is able to receive light through the opening of the first light-shielding layer. The charge generation region of the second unit is covered with a second light-shielding layer.

A first region includes a plurality of first transfer column regions distributed in a first direction. A second region includes a plurality of second transfer column regions distributed in the first direction. The second region is positioned downstream of the first region in a charge transfer direction in the second transfer section. Lengths in a second direction of the plurality of first transfer column regions are equal. Lengths in the second direction of the plurality of second transfer column regions are longer than the length of the first transfer column region, and increase as the second transfer column region is positioned downstream in the charge transfer direction. A third region is disposed to correspond to the first region and extends along the first direction. A fourth region is disposed to correspond to the second region and extends such that an interval between the fourth region and a pixel region in the second direction increases in the charge transfer direction in response to a change in the lengths of the plurality of second transfer column regions.

A first region includes first transfer column regions distributed in a first direction. A second region includes second transfer column regions distributed in the first direction. The second region is positioned downstream of the first region in a charge transfer direction. Lengths in a second direction of the first transfer column regions are equal. Lengths in the second direction of the second transfer column regions are longer than the length of the first transfer column region, and increase as the second transfer column region is positioned downstream in the charge transfer direction. A third region is disposed to correspond to the first region and extends along the first direction. A fourth region is disposed to correspond to the second region and extends such that an interval between the fourth region and a pixel region increases in response to a change in the lengths of the second transfer column regions.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors and alignment marks; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.

An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors and alignment marks; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the second level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.

An imaging system may include an array of image sensor pixels, each image sensor pixel including a photosensitive element coupled to time trace generation circuitry having a first CCD register. The time trace generation circuitry may be coupled to integration circuitry having a second integration CCD register via corresponding charge transfer structures. The second integration CCD register may integrate multiples sets of sampled charge from the first CCD register to improve the signal-to-noise ratio of the collected time trace information. The time trace generations circuitry or integration circuitry may also include background light subtract capabilities to remove background light level from the collected time trace information.

A photoelectric conversion apparatus includes a plurality of units each including a charge generation region disposed in a semiconductor layer. Each of a first unit and a second unit of the plurality of units includes a charge storage region configured to store charges transferred thereto from the charge generation region, a dielectric region located above the charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the charge storage region that is located between the insulator layer and the semiconductor layer, and the first light-shielding layer having an opening located above the charge generation region. The charge generation region of the first unit is able to receive light through the opening of the first light-shielding layer. The charge generation region of the second unit is covered with a second light-shielding layer.

A photoelectric conversion apparatus includes a plurality of units each including a charge generation region disposed in a semiconductor layer. Each of a first unit and a second unit of the plurality of units includes a charge storage region configured to store charges transferred thereto from the charge generation region, a dielectric region located above the charge generation region and surrounded by an insulator layer, and a first light-shielding layer covering the charge storage region that is located between the insulator layer and the semiconductor layer, and the first light-shielding layer having an opening located above the charge generation region. The charge generation region of the first unit is able to receive light through the opening of the first light-shielding layer. The charge generation region of the second unit is covered with a second light-shielding layer.