A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×10.sup.15 cm.sup.−3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.

Example embodiments relate to image sensors for time delay and integration imaging and methods for imaging using an array of photo-sensitive elements. One example image sensor for time delay and integration imaging includes an array of photo-sensitive elements that includes a plurality of photo-sensitive elements arranged in rows and columns of the array. Each photo-sensitive element includes an active layer configured to generate charges in response to incident light on the active layer. Each photo-sensitive element also includes a charge transport layer. Further, each photo-sensitive element includes at least a first and a second gate, each separated by a dielectric material from the charge transport layer. The array of photo-sensitive elements is configured such that the second gate of a first photo-sensitive element and the first gate of a second photo-sensitive element in a direction along a column of the array are configured to control transfer of charges.

The disclosure relates to a demodulator including a pinned photodiode, at least one storage node, at least one transfer gate connected between the storage node and the pinned photodiode. The pinned photodiode includes a p-doped epitaxial semiconductor layer, a n-doped semiconductor region formed within the epitaxial semiconductor layer and creating therewith a lower junction and at least one lateral junction substantially perpendicular to the lower junction, a p+ pinning layer formed on top of said semiconductor region. The demodulator further includes a generating unit configured to generate minority and majority carriers at said lateral junction and to form a lateral photodiode.

The present description concerns a photosite including: a photoconversion area configured to convert light into charges; at least one assembly of a first node and of a first charge flow path including a first switch configured to allow the flowing of charges from the photoconversion area to the first node of said assembly when said first switch is on and block the passage of charges between the photoconversion area and the first node of said assembly when said first switch is off; and a second charge flow path between said photoconversion area and a second node of the photosite, wherein the first and second paths are configured so that each first path holds the priority over the second path when the first switch of said first path is on.

A photo-detecting apparatus is provided. The photo-detecting apparatus includes: a substrate made by a first material or a first material-composite; an absorption layer made by a second material or a second material-composite, the absorption layer being supported by the substrate and the absorption layer including: a first surface; a second surface arranged between the first surface and the substrate; and a channel region having a dopant profile with a peak dopant concentration equal to or more than 1×10.sup.15 cm.sup.−3, wherein a distance between the first surface and a location of the channel region having the peak dopant concentration is less than a distance between the second surface and the location of the channel region having the peak dopant concentration, and wherein the distance between the first surface and the location of the channel region having the peak dopant concentration is not less than 30 nm.

A solid-state image sensor including photoelectric conversion parts having a vertical overflow drain structure is made usable as, for example, a distance measuring sensor with high accuracy. In the solid-state image sensor, a pixel array part is formed in a well region of a second conductive type formed at a surface part of a semiconductor substrate of a first conductive type. In the pixel array part, photoelectric conversion parts each of which converts incident light into signal charges and has the vertical overflow drain structure (VOD) are arranged in a matrix form. Substrate discharge pulse signal φSub for controlling potential of the VOD is applied to a signal terminal. An impurity induced part into which impurity of the first type is induced is formed below a connecting part in the semiconductor substrate.

An image sensor may include a pixel array, row control circuitry, and column readout circuitry. The row control circuitry may operate the pixel array in a global shutter mode of operation. In particular, timing control circuitry may provide global timing clock signals associated with a global photodiode reset event and a global photodiode charge transfer event to row driver circuitry providing control signals to each row in the array. Each driver circuitry may include a time delay circuit that delays the global timing clock signal by different amounts across the rows. Therefore, these global events may be offset on a per-row or per-row group basis, thereby mitigating power surges associated with global events. Further, by offsetting the global photodiode reset and charge transfer events using the same delay for a given row, the same global integration time may be preserved across different rows.

The invention relates to a detection apparatus (12) for detecting photons. The detection apparatus comprises a pile-up determining unit (15) for determining whether detection signal pulses being indicative of detected photons are caused by a pile-up event or by a non-pile-up event, wherein a detection values generating unit (16) generates detection values depending on the detection signal pulses and depending on the determination whether the respective detection signal pulse is caused by a pile-up event or by a non-pile-up event. In particular, the detection values generating unit can be adapted to reject the detection signal pulses caused by pile-up events while generating the detection values. This allows for an improved quality of the generated detection values.

Example embodiments relate to image sensors for time delay and integration imaging and methods for imaging using an array of photo-sensitive elements. One example image sensor for time delay and integration imaging includes an array of photo-sensitive elements that includes a plurality of photo-sensitive elements arranged in rows and columns of the array. Each photo-sensitive element includes an active layer configured to generate charges in response o incident light on the active layer. Each photo-sensitive element also includes a charge transport layer. Further, each photo-sensitive element includes at least a first and a second gate, each separated by a dielectric material from the charge transport layer. The array of photo-sensitive elements is configured such that the second gate of a first photo-sensitive element and the first gate of a second photo-sensitive element in a direction along a column of the array are configured to control transfer of charges.

The invention relates to a TDI line detector (1), comprising n TDI lines (Z1-Zn), wherein each TDI line (Z) has m pixels (P), and at least one read-out electronics (11-14), wherein the TDI line detector (1) is subdivided into x submodules (S1-S4), wherein the number of lines (Z) of a submodule (S1-S4) is n/x, wherein a discrete read-out electronics (11-14) is associated with the last line of each submodule (S1-S4), wherein the length (L1) of the read-out electronics (11-14) corresponds to an integer multiple of the length (L2) of a pixel (P), wherein x≥2 is, wherein the associated pixels (P) of different submodules (S1-S4) are arranged pixel to pixel relative to one another or the submodules (S1-S4) or groups of submodules (S1-S4) are laterally interlinked alternately by half a pixel (P).