Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.

Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

An analog-to-digital converter, including a sample/hold circuit; a reference voltage driver; a digital-to-analog converter; a comparator; and a logic circuit, wherein the reference voltage driver includes: a first voltage supplier circuit configured to output an external supply voltage provided from outside of the analog-to-digital converter; a second voltage supplier circuit configured to output a sampled reference voltage that is obtained during a sampling phase based on control signals received from the logic circuit; and a switching driver configured to electrically connect the first voltage supplier circuit to the digital-to-analog converter during a first conversion phase after the sampling phase based on the control signals received from the logic circuit, and to electrically connect the second voltage supplier circuit to the digital-to-analog converter during a second conversion phase based on the control signals received from the logic circuit.

High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.

An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

An analog-to-digital converter (ADC) and an operation method thereof are provided. The ADC includes: a comparator which compares a signal input through a first input terminal and a signal input through a second input terminal, and outputs an output value according to the comparison result. A successive approximation register receives the output value of the comparator, sets digital signal values from a most significant bit to a least significant bit, and outputs the digital signal values. A digital-to-analog converter receives the digital signal values, and converts it into an analog signal based on a reference voltage Vref, and outputs it to the second input terminal. A noise component is added to the input signal and to the analog signal Vdac′.

A semiconductor device with reduced power consumption can be provided. The semiconductor device includes a first transistor and a second transistor. The first transistor is a p-channel transistor including silicon in a channel formation region and the second transistor is an n-channel transistor including a metal oxide in a channel formation region. The metal oxide includes indium, an element M (e.g., gallium), and zinc. A gate of the first transistor is electrically connected to a gate of the second transistor, and one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The first transistor and the second transistor can each operate in a subthreshold region.

An ADC device includes a DAC circuit, a comparator circuit, a SAR decision circuit, an oscillator circuit having a delay unit, and a processing circuit. The oscillator circuit is used for generating the clock signal according to a reset signal and a delay of the delay unit. The processing circuit is used for sequentially generating multiple bit conversion signals associated with multiple different bits of the decision signal, for generating at least one guard signal which follows the multiple bit conversion signals, and then for comparing the at least one guard signal with the reset signal to adjust the delay generated by the delay unit of the oscillator circuit.

An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.