A self-aligned short-channel SASC electronic device includes a first semiconductor layer formed on a substrate; a first metal layer formed on a first portion of the first semiconductor layer; a first dielectric layer formed on the first metal layer and extended with a dielectric extension on a second portion of the first semiconductor layer that extends from the first portion of the first semiconductor layer, the dielectric extension defining a channel length of a channel in the first semiconductor layer; and a gate electrode formed on the substrate and capacitively coupled with the channel. The dielectric extension is conformally grown on the first semiconductor layer in a self-aligned manner. The channel length is less than about 800 nm, preferably, less than about 200 nm, more preferably, about 135 nm.

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.

A method of making N-type semiconductor layer includes following steps. An insulating substrate is provided. An MgO layer is deposited on the insulating substrate. A first dielectric layer is formed by acidizing the MgO layer. A semiconductor carbon nanotube layer is formed to cover the MgO layer. A source electrode and drain electrode are formed to be electrically connected to the semiconductor carbon nanotube layer. A second dielectric layer is applied on the semiconductor carbon nanotube layer. A gate electrode is formed on the second dielectric layer.

A semiconductor sensor includes an insulating substrate, a semiconductor sheet on the insulating substrate and including graphene or carbon nanotubes, a source electrode and a drain electrode, each being provided on the insulating substrate and electrically coupled to the semiconductor sheet, an oxide film extending over a surface of the semiconductor sheet and including silica, alumina, or a composite oxide of silica and alumina, and a receptor at a surface of the oxide film.

In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a D.sub.it of about 5e.sup.10 cm.sup.−2eV.sup.−1 to about 5e.sup.11 cm.sup.−2eV.sup.−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including CNTs embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

A method of making N-type semiconductor layer includes following steps. A semiconductor carbon nanotube layer is provided. A hafnium oxide layer is deposited on the semiconductor carbon nanotube layer via atomic layer deposition, wherein the atomic layer deposition includes following substeps. The semiconductor carbon nanotube layer is located into an atomic layer deposition system. The semiconductor carbon nanotube layer is heated to a temperature ranging from about 140° C. to about 200° C. A protective gas is continuously introduced into the atomic layer deposition system. The hafnium oxide layer is formed on the semiconductor carbon nanotube layer via introducing hafnium source and water vapor one by one into the atomic layer deposition system in a pulse manner.

Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.