Patent classifications
H10K10/474
Pentacene organic field-effect transistor with n-type semiconductor interlayer and its application
A method for enhancing the performance of pentacene organic field-effect transistor (OFET) using n-type semiconductor interlayer: an n-type semiconductor thin film was set between the insulating layer and the polymer electret in the OFET with the structure of gate-electrode/insulating layer/polymer/pentacene/source (drain) electrode. The thickness of n-type semiconductor layer is 1˜200 nm. The induced electrons at the interface of n-type semiconductor and polymer electret lead to the reduction of the height of the hole-barrier formed at the interface of polymer and pentacene, thus effectively reducing the programming/erasing (P/E) gate voltages of pentacene OFET, adjusting the height of hole barrier at the interface of polymer and pentacene to a reasonable scope by controlling the quantity of induced electrons in n-type semiconductor layer, thus improving the performance of pentacene OFET, such as the P/E speeds, P/E endurance and retention characteristics.
Transistors with Channels Formed of Low-Dimensional Materials and Method Forming Same
A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
π-conjugated boron compound, electronic device, and methods respectively for producing triarylborane and intermediate thereof
There are provided a π-conjugated boron compound, an electronic device containing an organic functional layer including the π-conjugated boron compound, a method for producing a triarylborane, and a method for producing a triarylborane intermediate. In the π-conjugated boron compound, a boron atom is bonded to three aromatic groups via three boron-carbon bonds. Bond distances of the three boron-carbon bonds are all 1.48 Å or less.
THIN FILM TRANSISTOR AND FILTER USING THIN FILM TRANSISTOR
A thin film transistor includes a gate electrode, a gate insulating layer, a carbon nanotube structure, a source electrode and a drain electrode. The gate insulating layer is located on the gate electrode. The carbon nanotube structure is located on the gate insulating layer. The source electrode and the drain electrode are arranged at intervals and electrically connected to the carbon nanotube structure respectively. The thin film transistor further includes an interface charge layer, and the interface charge layer is located between the carbon nanotube structure and the gate insulating layer.
PRODUCTION METHOD FOR PATTERNED ORGANIC FILM, PRODUCTION APPARATUS FOR PATTERNED ORGANIC FILM, ORGANIC SEMICONDUCTOR DEVICE PRODUCED BY SAME, AND INTEGRATED CIRCUIT INCLUDING ORGANIC SEMICONDUCTOR DEVICE
A method for producing a patterned organic film includes: forming a hydrophobic organic film on a hydrophilic and non-water-soluble first substrate using a coating method, pressing the organic film formed on the first substrate against a convex portion of a stamp having the convex portion and a concave portion, transferring the organic film to the convex portion by applying water or an aqueous solution to an interface between the first substrate and the organic film, and pressing the organic film transferred to the convex portion against a second substrate to transfer the organic film to the second substrate to obtain a patterned organic film, wherein at least one of the organic film and the second substrate is an organic semiconductor.
Patterning method for preparing top-gate, bottom-contact organic field effect transistors
The present invention relates to a process for the preparation of a top-gate, bottom-contact organic field effect transistor on a substrate, which organic field effect transistor comprises source and drain electrodes, a semiconducting layer, a cured first dielectric layer and a gate electrode, and which process comprises the steps of: i) applying a composition comprising an organic semiconducting material to form the semiconducting layer, ii) applying a composition comprising a first dielectric material and a crosslinking agent carrying at least two azide groups to form a first dielectric layer, iii) curing portions of the first dielectric layer by light treatment, iv) removing the uncured portions of the first dielectric layer, and v) removing the portions of the semiconducting layer that are not covered by the cured first dielectric layer, wherein the first dielectric material comprises a star-shaped polymer consisting of at least one polymer block A and at least two polymer blocks B, wherein each polymer block B is attached to the polymer block A, and wherein at least 60 mol % of the repeat units of polymer block B are selected from the group consisting of Formulas (1A), (1B), (1C), (1D), (1E) and (1F), wherein R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5, R.sup.6, R.sup.7 and R.sup.8 are independently and at each occurrence H or C.sub.1-C.sub.10-alkyl. ##STR00001##
SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
According to one embodiment, a semiconductor device includes a first insulating film, a first semiconductor layer formed of polycrystalline silicon, a second semiconductor layer formed of an oxide semiconductor, a second insulating film, a first gate electrode, a second gate electrode, a third insulating film formed of silicon nitride, and a protection layer. The protection layer is located between the second insulating film and the third insulating film, is opposed to the second semiconductor layer, and is formed of either an aluminum oxide or fluorinated silicon nitride.
Semiconductor device having an oxide semiconductor film and a metal oxide film
The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film. An insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is further formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. The oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by removing impurities such as hydrogen, moisture, a hydroxyl group, and hydride from the oxide semiconductor and supplying oxygen which is a major constituent of the oxide semiconductor and is simultaneously reduced in a step of removing impurities.
FIELD EFFECT TRANSISTOR STRUCTURE
A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.
Method of making N-type thin film transistor
A method of making N-type semiconductor layer includes following steps. An insulating substrate is provided. A semiconductor carbon nanotube layer is formed on the insulating substrate. An MgO layer is deposited on the semiconductor carbon nanotube layer. A functional dielectric layer is located on the MgO layer. A source electrode and drain electrode are formed to electrically connect the semiconductor carbon nanotube layer. A gate electrode is formed on the functional dielectric layer.