A nanowire array structure having an array of nanopillars located in a well in a material layer. The nanopillars of the array extend in the direction from the well floor towards the well mouth. A hard mask overlies the outer peripheral nanopillars in the array and extends outwards to cover the remainder of the well mouth. An aperture in the hard mask exposes the nanopillars disposed inwardly of the outer peripheral nanopillars. The hard mask planarizes the structure, avoiding formation of large topological features at the periphery of the array of nanopillars, thus facilitating integration of the structure into a semiconductor product. At least some of the outer peripheral nanopillars may be in pores of anodic oxide. There are also disclosed semiconductor products incorporating such nanowire array structures and methods of their fabrication.

A multilayer electronic component includes a body including a plurality of internal electrodes and a dielectric layer interposed between the plurality of internal electrodes; external electrodes disposed on the body, connected to the plurality of internal electrodes, and including electrode layers and plating layers respectively covering the electrode layers; and coating layers respectively covering the plating layer and including an island region exposing a portion of a surface of the plating layer.

A multilayer electronic component includes a body including a plurality of internal electrodes and a dielectric layer interposed between the plurality of internal electrodes; external electrodes disposed on the body, connected to the plurality of internal electrodes, and including electrode layers and plating layers respectively covering the electrode layers; and coating layers respectively covering the plating layer and including an island region exposing a portion of a surface of the plating layer.

A multilayer ceramic electronic component includes a body including a dielectric layer and an internal electrode, and an external electrode disposed on the exterior of the body. The dielectric layer includes a plurality of dielectric grains and a grain boundary present between the dielectric grains. A molar ratio (Al/Ti) of Al and Ti included in the grain boundary satisfies 0.022 to 0.028.

A multilayer ceramic electronic component includes a body including a dielectric layer and an internal electrode, and an external electrode disposed on the exterior of the body. The dielectric layer includes a plurality of dielectric grains and a grain boundary present between the dielectric grains. A molar ratio (Al/Ti) of Al and Ti included in the grain boundary satisfies 0.022 to 0.028.

An electrical device that includes: a metal barrier layer; an anodic porous oxide region on the metal barrier layer; a trench around the anodic porous oxide region reaching the metal barrier layer; a liner at least on a wall of the trench on a side of the anodic porous oxide region forming an electrical isolation barrier and having an opening onto the anodic porous oxide region; a hard mask arranged above the trenches and the liner having an opening onto the anodic porous oxide region. A corresponding manufacturing method is also disclosed.

The present invention relates to the urea of micro- and nanoelectronics and relates to ultra-compact micro capacitors, how they can he used, for example, in electrical and electronic devices. The object of the present invention consists in specifying an ultra-compact micro capacitor with the highest capacity. The problem is solved by an ultra-compact micro capacitor which is made from a rolled-up layer stack of alternatingly arranged layers of dielectric and/or electrically insulating and electrically conductive materials with rolled-up lengths of the layer stack of at least 1 mm, and an absolute electrical storage capacity of at least 10 nF. The problem is additionally solved by a method, in which a layer containing a water-soluble cellulose derivative is applied to a substrate and a layer stack to same, the layer containing the cellulose derivative is removed from the substrate using Nuttier, an organic solvent and/or an organic solvent mixture, and the layer stack is rolled up with a rolling speed of more than 0.1 mm/min.

The present invention relates to the urea of micro- and nanoelectronics and relates to ultra-compact micro capacitors, how they can he used, for example, in electrical and electronic devices. The object of the present invention consists in specifying an ultra-compact micro capacitor with the highest capacity. The problem is solved by an ultra-compact micro capacitor which is made from a rolled-up layer stack of alternatingly arranged layers of dielectric and/or electrically insulating and electrically conductive materials with rolled-up lengths of the layer stack of at least 1 mm, and an absolute electrical storage capacity of at least 10 nF. The problem is additionally solved by a method, in which a layer containing a water-soluble cellulose derivative is applied to a substrate and a layer stack to same, the layer containing the cellulose derivative is removed from the substrate using Nuttier, an organic solvent and/or an organic solvent mixture, and the layer stack is rolled up with a rolling speed of more than 0.1 mm/min.

[Problem] Provided is an oxide dielectric having superior properties, and a solid state electronic device (for example, a high pass filter, a patch antenna, a capacitor, a semiconductor device, or a microelectromechanical system) including the oxide dielectric.

[Solution] The oxide layer 30 according to the present invention includes an oxide (possibly including inevitable impurities) consisting essentially of bismuth (Bi) and niobium (Nb) and having a crystal phase of the pyrochlore-type crystal structure, in which the number of atoms of the above niobium (Nb) is 1.3 or more and 1.7 or less when the number of atoms of the above bismuth (Bi) is assumed to be 1.

[Problem] Provided is an oxide dielectric having superior properties, and a solid state electronic device (for example, a high pass filter, a patch antenna, a capacitor, a semiconductor device, or a microelectromechanical system) including the oxide dielectric.

[Solution] The oxide layer 30 according to the present invention includes an oxide (possibly including inevitable impurities) consisting essentially of bismuth (Bi) and niobium (Nb) and having a crystal phase of the pyrochlore-type crystal structure, in which the number of atoms of the above niobium (Nb) is 1.3 or more and 1.7 or less when the number of atoms of the above bismuth (Bi) is assumed to be 1.