A multilayer ceramic capacitor includes a multilayer body including dielectric layers which are stacked and internal electrode layers which are stacked, and external electrodes, each connected to the internal electrode layers. The external electrodes each include a conductive resin layer and a plated layer on the conductive resin layer. The conductive resin layer includes a resin portion, conductive fillers dispersed in the resin portion, and metal particles dispersed unevenly in a distribution differing from that of the conductive fillers in the conductive resin layer. An abundance ratio of the metal particles to the resin portion is higher on a side of the plated layer of the conductive resin layer than on a side of the conductive resin layer close to the multilayer body.

An electronic device includes a plurality of chip components and an insulating case. The chip components are arranged in a first direction. The case includes a plate portion, a first protrusion portion, and a second protrusion portion. The plate portion faces first side surfaces of the chip components. The first protrusion portion is formed along a plate-portion first side of the plate portion and protrudes from the plate portion toward a downside perpendicular to the first direction. The second protrusion portion is formed to the first protrusion portion in a second direction and protrudes from the plate portion toward the downside. A protrusion length of the first protrusion portion and the second protrusion portion from the plate portion toward the downside is smaller than a protrusion length of the chip component included in the chip components from the plate portion toward the downside.

A multilayer ceramic electronic component includes: a ceramic body including dielectric layers and first internal electrodes and second internal electrodes disposed to face each other and alternately stacked with the respective dielectric layers interposed therebetween; a first external electrode connected to the first internal electrodes; a second external electrode connected to the second internal electrodes; and a protective layer disposed on the ceramic body, the first external electrode, and the second external electrode, wherein the protective layer includes an adhesion assisting layer and a coating layer.

An AIMD includes a conductive housing, an electrically conductive ferrule with an insulator hermetically sealing the ferrule opening. A conductive pathway is hermetically sealed and disposed through the insulator. A filter capacitor is disposed on a circuit board within the housing and has a dielectric body supporting at least two active and two ground electrode plates interleaved, wherein the at least two active electrode plates are electrically connected to the conductive pathway on the device side, and the at least two ground electrode plates are electrically coupled to either the ferrule and/or the conductive housing. The dielectric body has a dielectric constant less than 1000 and a capacitance of between 10 and 20,000 picofarads. The filter capacitor is configured for EMI filtering of MRI high RF pulsed power by a low ESR, wherein the ESR of the filter capacitor at an MRI RF pulsed frequency or range of frequencies is less than 2.0 ohms.

An AIMD includes a conductive housing, an electrically conductive ferrule with an insulator hermetically sealing the ferrule opening. A conductive pathway is hermetically sealed and disposed through the insulator. A filter capacitor is disposed on a circuit board within the housing and has a dielectric body supporting at least two active and two ground electrode plates interleaved, wherein the at least two active electrode plates are electrically connected to the conductive pathway on the device side, and the at least two ground electrode plates are electrically coupled to either the ferrule and/or the conductive housing. The dielectric body has a dielectric constant less than 1000 and a capacitance of between 10 and 20,000 picofarads. The filter capacitor is configured for EMI filtering of MRI high RF pulsed power by a low ESR, wherein the ESR of the filter capacitor at an MRI RF pulsed frequency or range of frequencies is less than 2.0 ohms.

The capacitor includes a dielectric body portion including ceramic layers and internal-electrode layers laminated in an alternating manner, and a cover portion provided in a periphery of the dielectric body portion. The cover portion includes pores. A part of the cover portion located in a position in a direction perpendicular to a lamination direction of the ceramic layers and the internal-electrode layers is a side surface cover portion. When the side surface cover portion is divided into three equal regions in a width direction, the regions being a dielectric body portion-side region, a central region, and a surface-side region, the number of the pores is higher in the dielectric body portion-side region than in the central region and the surface-side region.

A method of producing a dielectric material by preparing a slurry by mixing a dielectric powder, water, one of an organic-acid metal salt and an inorganic metal salt, and an organic silicon compound, causing the slurry to come into contact with an anion exchange resin to remove an anion derived from the one of the organic-acid metal salt and the inorganic metal salt from the slurry, and drying the slurry to obtain the dielectric material.

A method of producing a dielectric material by preparing a slurry by mixing a dielectric powder, water, one of an organic-acid metal salt and an inorganic metal salt, and an organic silicon compound, causing the slurry to come into contact with an anion exchange resin to remove an anion derived from the one of the organic-acid metal salt and the inorganic metal salt from the slurry, and drying the slurry to obtain the dielectric material.

A multilayer electronic component that includes a stacked body having therein a plurality of dielectric layers including a CZ-based perovskite phase and an element M1, a plurality of internal electrode layers including Cu, and an interface layer including the element M1 in at least a portion of an interface with the plurality of internal electrode layers. Element M1 is an element that has a binding energy between CZ and Cu via the element M1 of less than or equal to −9.8 eV by first-principles calculation using a pseudopotential method. When amounts of elements included in the dielectric layers are expressed as parts by mol, a ratio m1 of an amount of the element M1 to an amount of the Zr in the interface layer is 0.03≤m1≤0.25.

A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.