An electronic component includes a multilayer body including a multilayer main body including end surfaces at which internal nickel electrode layers are exposed, side gap portions, external nickel layers on the end surfaces of the multilayer body, and external copper electrode layers covering the end surfaces on which the external nickel layers are provided. A nickel-based oxide and/or a silicon-based oxide are provided between the external nickel layer and the external copper electrode layer. A nickel layer and a tin layer are provided outside the external copper electrode layer. In a cross section passing through a middle of the electronic component in the width direction and extending in the length direction and the lamination direction, a relationship of about 0.2≤Tea/Tem≤about 1.1 is satisfied.

The present invention relates to the urea of micro- and nanoelectronics and relates to ultra-compact micro capacitors, how they can he used, for example, in electrical and electronic devices. The object of the present invention consists in specifying an ultra-compact micro capacitor with the highest capacity. The problem is solved by an ultra-compact micro capacitor which is made from a rolled-up layer stack of alternatingly arranged layers of dielectric and/or electrically insulating and electrically conductive materials with rolled-up lengths of the layer stack of at least 1 mm, and an absolute electrical storage capacity of at least 10 nF. The problem is additionally solved by a method, in which a layer containing a water-soluble cellulose derivative is applied to a substrate and a layer stack to same, the layer containing the cellulose derivative is removed from the substrate using Nuttier, an organic solvent and/or an organic solvent mixture, and the layer stack is rolled up with a rolling speed of more than 0.1 mm/min.

A semiconductor device includes: a first electrode; a second electrode; and a multi-layered stack including a hafnium oxide layer of a tetragonal crystal structure which is positioned between the first electrode and the second electrode, wherein the multi-layered stack includes: a seed layer for promoting tetragonal crystallization of the hafnium oxide layer and having a tetragonal crystal structure; and a booster layer for boosting a dielectric constant of the hafnium oxide layer.

A capacitor assembly and a method of assembling a capacitor assembly are provided. The capacitor assembly has at least two capacitor stacks, which have a layer structure including a top layer and a bottom layer. A support assembly supports the capacitor stacks. The capacitor stacks are stacked on top of each other in the support assembly. The support assembly has a compression member which compresses the at least two capacitor stacks in a direction substantially perpendicular to the layer structure. A pressure distribution arrangement adjusts the distribution of the pressure applied to the capacitor stacks by the compression member.

The present invention ultra-low loss high energy density dielectric layers having femtosecond (10.sup.−15 sec) polarization response times within a chip stack assembly to extend impedance-matched electrical lengths and mitigate ringing within the chip stack to bring the operational clock speed of the stacked system closer to the intrinsic clock speed(s) of the semiconductor die bonded within chip stack.

In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V.sup.2; and a capacitor second plate over the dielectric stack.

A capacitor includes: a plurality of bottom electrodes; a dielectric layer formed over the bottom electrodes; and a top electrode formed over the dielectric layer, wherein the top electrode includes a carbon-containing material and a germanium-containing material that fill a gap between the bottom electrodes.

A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.

An electronic component including a substrate, a capacitor lower electrode disposed on the substrate, an inorganic dielectric layer disposed on the substrate to cover the lower electrode, a capacitor upper electrode disposed directly on the inorganic dielectric layer and facing the lower electrode via the inorganic dielectric layer, and a coil electrically connected to the lower electrode or the upper electrode. The upper surface of the inorganic dielectric layer is flat.

An electronic component including a substrate, a capacitor lower electrode disposed on the substrate, an inorganic dielectric layer disposed on the substrate to cover the lower electrode, a capacitor upper electrode disposed directly on the inorganic dielectric layer and facing the lower electrode via the inorganic dielectric layer, and a coil disposed on the inorganic dielectric layer and electrically connected to the lower electrode or the upper electrode.