A capacitor packaging having a central termination and three or more capacitors (or groups of capacitors) arranged about the central termination. The electrical flow paths between the termination and the capacitors or groups of capacitors are of substantially the same length. The capacitors or groups of capacitors may be arranged in a generally circular pattern with the termination centered on the center. The termination may include first and second terminals. The capacitors may be mounted to a printed circuit board (“PCB”) with traces on opposite surfaces of the PCB providing electrical flow paths from the terminals to opposite legs of the capacitors. The capacitor packaging may include a primary PCB with a first circular arrangement of capacitors and a secondary PCB with a second circular arrangement of capacitors. The capacitors may be sandwiched between the PCBs with the second arrangement of capacitors disposed concentrically inwardly of the first arrangement.

New types of circuit elements for integrated circuits include structures wherein a thickness dimension is much greater than a width dimension and is more closely spaced than the width dimension in order to attain a tight coupling condition. The structure is suitable to form inductors, capacitors, transmission lines and low impedance power distribution networks in integrated circuits. The width dimension is on the same order of magnitude as skin depth. Embodiments include a spiral winding disposed in a silicon substrate formed of a deep, narrow, conductor-covered spiral ridge separated by a narrow spiral trench. Other embodiments include a wide, thin conductor formed in or on a flexible insulative ribbon and wound with turns adjacent one another, or a conductor in or on a flexible insulative sheet folded into layers with windings adjacent one another Further, a method of manufacture includes directional etching of the deep, narrow spiral trench to form a winding in silicon.

A dielectric composition includes main phases and Ca-RE-Si—O segregation phases. The main phases include a main component expressed by ABO.sub.3. “A” includes at least one selected from barium and calcium. “B” includes at least one selected from titanium and zirconium. “RE” represents at least one of rare earth elements. A molar ratio of (Si/Ca) is larger than one. A molar ratio of (Si/RE) is larger than one, provided that the molar ratio of (Si/RE) is a molar ratio of silicon included in the segregation phases to the rare earth elements included therein. An average length of major axes of the segregation phases is 1.30-2.80 times as large as an average particle size of the main phases. An average length of minor axes of the segregation phases is 0.21-0.48 times as large as an average particle size of the main phases.

A multilayer ceramic capacitor includes a laminated body in which dielectric layers and internal electrodes are laminated alternately. The dielectric layer includes a first phase that contains calcium strontium zirconate titanate as a main component thereof and a second phase that contains barium zirconate as a main component thereof. At a cross section of the dielectric layer, a line parallel to the direction in which the dielectric layers and the internal electrodes are laminated contacts the boundaries between the first phase and the second phase once or more on average, thereby the statistically averaged contact number N of such a line with the boundaries determined by a prescribed procedure being 1.0 or greater.

A dielectric composition includes a dielectric grain including a perovskite compound and a first segregation phase including at least Ca, Al, Si, and O.

A ceramic electronic device includes a multilayer structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked. Each of the plurality of dielectric layers includes ceramic grains of a main component thereof expressed by (Ba.sub.1−x−yCa.sub.xSr.sub.y)(Ti.sub.1−zZr.sub.z)O.sub.3 (0<x≤0.2, 0≤y≤0.1, 0≤z≤0.1). D3<D1<D2 is satisfied when an average grain diameter of the ceramic grains of the main component of the plurality of dielectric layers in a section in which each two internal electrode layers is D1, an average grain diameter of the ceramic grains of the main component of first dielectric layers which are located at different height positions from the internal electrode layers is D2, an average grain diameter of the ceramic grains of the main component of second dielectric layers which are located at same height positions of the internal electrode layers is D3.

A ceramic electronic component includes a body including a dielectric layer and an internal electrode, and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell surrounding at least a portion of the core, and a second shell surrounding at least a portion of the first shell, and a concentration of a rare earth element included in the second shell is more than 1.3 times to less than 3.8 times a concentration of a rare earth element included in the first shell.

A ceramic electronic component includes a body, including a dielectric layer and an internal electrode, and an external electrode disposed on the body and connected to the internal electrode. At least a region of the dielectric layer includes tin (Sn) and a lanthanide rare earth element (RE) including dysprosium (Dy). In the at least a region of the dielectric layer, a molar ratio of tin (Sn) to dysprosium (Dy) is from 0.15 to 0.30.

A ceramic electronic device includes a multilayer body in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. In at least a part of a cover layer and side margins, a concentration of a specific metal of at least one of Ag, As, Au, Bi, Co, Cr, Cu, Fe, Ge, In, Ir, Mo, Os, Pd, Pt, Re, Rh, Ru, Se, Sn, Te, W or Zn is lower on an outer side than on a side of the multilayer body.

A method of manufacturing a dielectric for a capacitor and a dielectric for a capacitor manufactured thereby are provided. A dielectric for a capacitor is prepared by calcining a precursor mixture containing lead, lanthanum, zirconium, and titanium to produce calcined powder, adding additives including sodium, potassium, and the like to the powder, and sintering the mixture at a low temperature, whereby the dielectric has a high density and a large dielectric constant.