Discussed is a method of manufacturing a LCD device, the method including: forming a gate in each of a plurality of pixel areas on a substrate; forming a gate insulator to cover the gate; forming a semiconductor layer on the gate insulator, and forming a photoresist (PR) on the semiconductor layer; doping high-concentration impurities at the semiconductor layer by using the photoresist (PR) as a mask to form an active layer, a source, and a drain; and doping low-concentration impurities at the semiconductor layer by using the photoresist (PR) as the mask to form a lightly doped drain (LDD) between the active layer and the source and between the active layer and the drain.

A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.

Discussed are a liquid crystal display (LCD) device and a method of manufacturing the LCD device. The LCD device can include a plurality of pixel areas defined by intersections of a plurality of gate lines and a plurality of data lines, a gate disposed in each of the plurality of pixel areas, a gate insulator disposed to cover the gate, an active layer disposed on only the gate with the gate insulator therebetween, a thin film transistor (TFT) configured to include a source, which is disposed at a first side of the active layer, and a drain disposed at a second side of the active layer, a pixel electrode connected to the drain of the TFT and configured to supply a data voltage to a corresponding pixel area, a common electrode configured to supply a common voltage to the corresponding pixel area, and a lightly doped drain (LDD) disposed between the active layer and the source and between the active layer and the drain. At least a portion of the LDD can be disposed on the gate.

A semiconductor device includes at least one thin film transistor (100, 200), the at least one thin film transistor including a semiconductor layer (3A, 3B) which includes a channel region (31A, 31), a high-concentration impurity region, and a low-concentration impurity region (32A, 32B) which is located between the channel region and the high-concentration impurity region, a gate electrode (7A, 7B) provided on a gate insulating layer (5), an interlayer insulating layer (11) provided on the gate electrode, and a source electrode (8A, 8B) and a drain electrode (9A, 9B), wherein the interlayer insulating layer and the gate insulating layer have a contact hole extending to the semiconductor layer, at least one of the source electrode (8A, 8B) and the drain electrode (9A, 9B) being in contact with the high-concentration impurity region inside the contact hole, at a side wall of the contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, and at an upper surface of the semiconductor layer, an edge of the contact hole aligned with an edge of the high-concentration impurity region.

A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a display device are provided. The TFT includes: a base substrate; a gate electrode and a gate insulating layer, disposed on the base substrate; and an active layer, wherein the gate insulating layer is disposed between the active layer and the gate electrode; the active layer includes a channel region and a doped region disposed on at least one side of the channel region; and the gate insulating layer is provided with a protrusion which is disposed between the doped region and the gate electrode.

A low temperature polysilicon (LTPS) thin film transistor (TFT) substrate and a method for manufacturing the same are provided. The method includes: sequentially forming a plurality of light-shielding portions, a buffer layer, and a plurality of island-shaped polysilicon portions on a substrate; performing light ion doping over two sides of the island-shaped polysilicon portions to form doped regions and channel regions; sequentially forming a gate insulating layer and a plurality of gate electrodes; performing heavy ion doping over the doped region that are not covered by the gate electrodes to form N-type heavily doped regions and N-type lightly doped regions; and forming an interlayer insulating layer as well as a source electrode and a drain electrode which are electrically connected to the N-type heavily doped regions on the gate electrodes.

A semiconductor device has a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode. A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20 s) or a drain region (20 d) can be reduced, resulting in diminished parasitic capacitance.

An integrated circuit device includes a first wiring, a second wiring, a semiconductor member that is connected between the first and second wirings, an electrode, and an insulating film that is provided between the semiconductor member and the electrode. The semiconductor member includes a first semiconductor portion of a first conductivity type connected to the first wiring, a second semiconductor portion of the first conductivity type, a third semiconductor portion of the first conductivity type, a fourth semiconductor portion of the first conductivity type, a fifth semiconductor portion of a second conductivity type, and a sixth semiconductor portion of the first conductivity type in this order. A first edge of the electrode on a side of the first wiring overlaps the second, third, or fourth semiconductor portions.

Present application provides a method of manufacturing a semiconductor structure, including forming a well, forming a gate electrode over the well, implanting a lightly doped region in a first side of the well, implanting a first drain in the lightly doped region by a first depth, implanting a second drain in the lightly doped region by a second depth, implanting a source in a second side of the well, the second side being opposite to the first side. The second depth is greater than the first depth. The gate electrode is formed to cover a part of the lightly doped region and a part of the first drain.

Present application provides a method of manufacturing a semiconductor structure, including forming a well, forming a gate electrode over the well, implanting a lightly doped region in a first side of the well, implanting a first drain in the lightly doped region by a first depth, implanting a second drain in the lightly doped region by a second depth, implanting a source in a second side of the well, the second side being opposite to the first side. The second depth is greater than the first depth. The gate electrode is formed to cover a part of the lightly doped region and a part of the first drain.