The present disclosure discloses a manufacturing method for an array substrate and an array substrate. The method includes: forming a gate electrode, a gate insulating layer, a semiconductor layer, a source drain electrode layer and a photoresist layer on a substrate; patterning the photoresist layer to form a patterned photoresist layer; performing at least one wet etching on the source drain electrode layer and performing at least one dry etching on the semiconductor layer; performing an ashing processing between the steps of the wet etching and the dry etching. A ratio of a lateral etching rate to a longitudinal etching rate in the at least one ashing processing ranges from 1:0.9 to 1:1.5.

The present application provides a thin film transistor having an active layer. The active layer includes a source electrode contact part, a drain electrode contact part, and a channel part between the source electrode contact part and the drain electrode contact part. The channel part includes at least a first portion and a second portion different from the first portion. The second portion has an enhanced ability to capture off-state leaking carriers as compared to the first portion.

Disclosed are a method and a device for manufacturing an array substrate, and an array substrate. The method includes: depositing and forming a gate insulation layer on a pre-formed base substrate and a pre-formed gate, the gate insulation layer covering the pre-formed gate; depositing and forming an amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer on the gate insulation layer in sequence, doping concentrations of the at least three doped layers of the doped amorphous silicon layer increasing from bottom to top; etching patterns of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer to form the array substrate.

This application provides a method for manufacturing an array substrate, an array substrate, and a display panel. A gate metal layer, a gate insulating layer, and a semiconductor active layer are formed by using one photomask process, a first passivation layer is formed in one photomask process, and a source metal layer, a drain metal layer, and a pixel electrode layer are formed on the first passivation layer.

In an example, a display device comprises a substrate with pixels arranged in a display portion, a signal line control circuit connected to signal lines, a plurality of thin film transistors inputting a pixel signal to a corresponding one of the pixels from the corresponding one of the signal lines, a common electrode overlapping the entire display portion, an insulating film disposed on the common electrode, a common line connected to the common electrode through contact holes in the insulating film, where the common line is disposed between the substrate and the insulating film, and outside the display portion along four sides of the display portion, a plurality of gate lines electrically connected to the thin film transistors, and a gate line control circuit connected to and configured to provide a gate signal to each of the gate lines, and disposed between the display portion and the common line.

A method of manufacturing array substrate and a display panel, wherein, the method of manufacturing array substrate includes: depositing a gate electrode, a gate insulation layer, a semiconductor layer, a metal layer and a photoresist; forming an non-exposure area, a partial exposure area and a full exposure area through exposure and developing; then, performing a first ashing treatment and a wet etching to form a metal layer recess, and performing a second ashing treatment to etch off residual photoresist which remains in the metal layer recess after the first ashing treatment; and finally performing a dry etching to form a pattern of a channel region.

A TFT substrate includes a transmission and/or reception region including a plurality of antenna unit regions, and a non-transmission and/or reception region located in a region other than the transmission and/or reception region. Each of the antenna unit regions U includes a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate includes a gate metal layer including a gate electrode of the TFT, a gate insulating layer, a source metal layer including a source electrode of the TFT and the drain electrode, a first insulating layer, a patch metal layer including the patch electrode, a second insulating layer, and an upper conductive layer. The upper conductive layer includes a patch drain connection section electrically connected to the patch electrode and the drain electrode.

A display device includes a substrate, a plurality of pixels above the substrate, each of the pixels including a light emitting element, a display region including the plurality of pixels, a thin film transistor which each of the plurality of pixels includes, a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element, a sealing film including a second inorganic insulating material and covering the light emitting element, and at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film, wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.

The present disclosure provides an array substrate and a method for manufacturing an array substrate. The array substrate includes a substrate, a switch assembly disposed on the substrate and correspondingly disposed beside the switch assembly, a color photoresist layer formed on the switch assembly and the photosensor, and a pixel electrode formed on the color photoresist layers and coupled with the switch assembly. The switch assembly includes a first metal layer. The photosensor includes a first electrode layer formed directly on the substrate and a first amorphous silicon layer disposed above the first electrode layer. The first electrode layer and the first metal layer are disposed on a same layer.

A display panel measures a contact resistance of an adhesive portion to evaluate adhesion quality of an integrated circuit mounted thereon. The display panel includes a plurality of light-emitting elements, a first pad part including a plurality of first effective pads electrically connected to the light-emitting elements, and n (n being a natural number equal to or greater than 2) first measuring pads insulated from the light-emitting elements, a conductive adhesive film on the first pad part and including a plurality of conductive balls, an integrated circuit on the conductive adhesive film, and including an internal line electrically connected to the first measuring pads by the conductive balls, and a second pad part including a plurality of second effective pads electrically connected to the first effective pads, and 2n second measuring pads electrically connected to the first measuring pads.