Disclosed is a thin film transistor, an array substrate, a method for manufacturing the same, and a display device. The method includes: forming a source and drain on a base substrate and forming a semiconductor layer. Between the step of forming the source and drain and the step of forming the semiconductor layer, the method further includes: forming a diffusion barrier layer. Metal atoms diffused from the source and drain and passing through the diffusion barrier layer react with a part of the semiconductor layer near the source and drain, and a metal transition layer containing metal silicide is formed.

A device includes a first stage having a first optical switch, a first transistor connected to the first optical switch, and a second transistor connected to the first optical switch and the first transistor. The device also includes a second stage having a second optical switch, a third transistor connected to the second transistor and the second optical switch, and a fourth transistor connected to the second transistor, the second optical switch, and the third transistor.

A thin film transistor is provided, and includes a gate electrode, a first gate dielectric layer, a second gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed on a substrate. The first gate dielectric layer is disposed on the gate electrode and the substrate, and has a radio of the number of silicon-hydrogen bonds to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.2 and 1.0. The second gate dielectric layer is disposed on the first gate dielectric layer, and has a radio of the number of silicon-hydrogen bond to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.01 and 0.2. The channel layer is disposed on the second gate dielectric layer. The source electrode and drain electrode are disposed on the channel layer and located at two opposite sides of the channel layer.

This disclosure provides a communication device and a manufacturing method thereof. The manufacturing method of the communication device includes the following steps: providing a first dielectric layer, wherein the first dielectric layer includes a first region and a second region, and the first dielectric layer has a first surface and a second surface opposite to the first surface; providing a second dielectric layer; combining the first dielectric layer and the second dielectric layer with a sealing element, so that the sealing element is disposed between the first surface of the first dielectric layer and a third surface of the second dielectric layer; after combining the first dielectric layer and the second dielectric layer, thinning the second surface of the first dielectric layer; and disposing a first communication element on the first surface of the first dielectric layer in the first region.

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

The present application provides an array substrate and a display panel. The array substrate includes a substrate and a thin film transistor layer. The thin film transistor layer includes a first metal layer and a second metal layer, the first metal layer includes at least one first metal trace, the second metal layer includes at least one second metal trace, the thin film transistor layer includes a trace crossover area, a barrier layer is disposed between the first metal layer and the second metal layer, and the barrier layer at least covers the trace crossover area.

The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a dual-gate transistor and a memory cell. The memory cell is adjacent to the dual-gate transistor, wherein the memory cell and the dual-gate transistor share a common electrode.

This liquid crystal display apparatus is provided with: a TFT substrate comprising a thin film transistor and a pixel electrode connected to the thin film transistor; and a counter substrate comprising a common electrode that faces the pixel electrode via a liquid crystal layer. The thin film transistor comprises: a semiconductor layer deposited over a gate electrode via a gate insulating layer, while having a planar shape that has a first side and a second side each overlapping the gate electrode in plan view; and a first electrode which is connected to the pixel electrode and a second electrode which faces the first electrode, said first and second electrodes being formed on the semiconductor layer. The first side and the second side of the semiconductor layer are adjacent to each other at a predetermined angle; and the first electrode at least partially covers the first side and the second side.

A thin film transistor substrate includes: a substrate; and a thin film transistor including a gate electrode on the substrate, an active layer on the gate electrode, and a source electrode and a drain electrode on the active layer. Within the thin film transistor, at least one of the source electrode and the drain electrode defines a plurality of branch electrodes thereof and a main electrode to which the plurality of branch electrodes is commonly connected. Each of the plurality of branch electrodes overlaps the gate electrode.

In a method of manufacturing a display substrate and a method of manufacturing a display panel, the display substrate includes a color filter layer disposed on a base substrate within a pixel area, a first organic insulating pattern disposed on a first boundary area between adjacent pixel areas, a pixel electrode disposed on the color filter layer, and a first blocking pattern disposed on the first organic insulating pattern. Accordingly, an organic insulating layer corresponding to the pixel area is removed so that deterioration of the display quality by impurities generated from the organic insulating layer may be minimized. In addition, a stepped portion of a blocking pattern disposed between a pixel area and a boundary area of a plurality of the pixel areas is reduced so that motion blurring of a liquid crystal may be prevented.