A wafer carrier assembly as described herein improves thermal control across a top surface thereof to maintain highly controlled deposition locations and thicknesses.

Embodiments of the disclosed technology include patterning a graphene sheet for biosensor and electronic applications using lithographic patterning techniques. More specifically, the present disclosure is directed towards the method of patterning a graphene sheet with a hard mask metal layer. The hard mask metal layer may include an inert metal, which may protect the graphene sheet from being contaminated or damaged during the patterning process.

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.

Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device.

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

An epitaxial wafer and a method of fabricating an epitaxial wafer, the method including providing a semiconductor substrate doped with both boron and germanium such that a sum of boron concentration and germanium concentration is at least 8.5E+18 atoms/cm.sup.3 and the germanium concentration is 6 times or less the boron concentration; forming an epitaxial layer on the semiconductor substrate such that the semiconductor substrate and the epitaxial layer constitute the epitaxial wafer; and annealing the epitaxial wafer for 1 hour or longer at a temperature of 1,000° C. or less.

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

The present disclosure relates to a method that includes directing a first precursor that includes a Group III element and a second precursor that includes a Group V element to a chamber containing crystalline silicon, where the crystalline silicon includes a substantially planar surface that is patterned with a plurality of v-grooves and the directing results in the forming of a III-V crystal preferentially on a (111) Si surface of the crystalline silicon.