Patent classifications
H01L21/02381
Semiconductor Structures
A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.
NITRIDE SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR
According to one embodiment, a nitride semiconductor includes a base body, a nitride member, and an intermediate region provided between the base body and the nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x1≤1), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0≤x2<1, x2<x1). The first nitride region is between the intermediate region and the second nitride region. The intermediate region includes nitrogen and carbon. A concentration of carbon in the intermediate region is not less than 1.5×10.sup.19/cm.sup.3 and not more than 6×10.sup.20/cm.sup.3.
GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY
Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.
NITRIDE SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR
According to one embodiment, a nitride semiconductor includes a base body, and a nitride member. The nitride member includes a first nitride region including Al.sub.x1Ga.sub.1-x1N (0<x1≤1), and a second nitride region including Al.sub.x2Ga.sub.1-x2N (0≤x2<1, x2<x1). The first nitride region is between the base body and the second nitride region. The first nitride region includes a first portion and a second portion. The second portion is between the first portion and the second nitride region. An oxygen concentration in the first portion is higher than an oxygen concentration in the second portion. The oxygen concentration in the second portion is not more than 1×10.sup.18/cm.sup.3. A first thickness of the first portion in a first direction from the first to second nitride regions is thinner than a second thickness of the second portion in the first direction.
Epitaxially coated semiconductor wafer of monocrystalline silicon and method for production thereof
A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.
Small pitch super junction MOSFET structure and method
The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.
Monolithic single chip integrated radio frequency front end module configured with single crystal acoustic filter devices
A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.
Field effect transistor using transition metal dichalcogenide and a method for forming the same
In a method of forming a two-dimensional material layer, a nucleation pattern is formed over a substrate, and a transition metal dichalcogenide (TMD) layer is formed such that the TMD layer laterally grows from the nucleation pattern. In one or more of the foregoing and following embodiments, the TMD layer is single crystalline.
Semiconductor thin film structures and electronic devices including the same
A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.
HETEROEPITAXIAL GROWTH METHOD OF COMPOUND SEMICONDUCTOR MATERIALS ON MULTI-ORIENTED SEMICONDUCTOR SUBSTRATES AND DEVICES
A method for growing a semiconductor material over a Si-based substrate includes providing the Si-based substrate; growing a monocrystalline refractory-metal ceramic film directly over the Si-based substrate; and depositing a semiconductor film directly over the monocrystalline refractory-metal ceramic film. The monocrystalline refractory-metal ceramic film has a thickness less than 300 nm.