A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate; forming a conformal SiN, SiO.sub.xC.sub.yN.sub.z layer over side and bottom surfaces of the first trenches; filling the first trenches with SiO.sub.x; forming a first mask over portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate; removing exposed portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate, forming second trenches; forming III-V, III-V.sub.xM.sub.y, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-V.sub.xM.sub.y, or Si nanowires and intervening first trenches; removing the SiO.sub.x layer, forming third trenches; and removing the second mask.

The present invention relates to a method for manufacturing a diamond substrate, and more particularly, to a method of growing diamond after forming a structure of an air gap having a crystal correlation with a lower substrate by heat treatment of a photoresist pattern and an air gap forming film material on a substrate such as sapphire (Al.sub.2O.sub.3). Through such a method, a process is simplified and the cost is lowered when large-area/large-diameter single crystal diamond is heterogeneously grown, stress due to differences in a lattice constant and a coefficient of thermal expansion between the heterogeneous substrate and diamond is relieved, and an occurrence of defects or cracks is reduced even when a temperature drops, such that a high-quality single crystal diamond substrate may be manufactured and the diamond substrate may be easily self-separated from the heterogeneous substrate.

A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is Hz, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.

According to a first aspect of the disclosure, there is provided a device comprising: a substrate comprising a III-V semiconductor having a crystalline surface; and a kagome lattice formed from atoms of an element with atomic number Z greater than or equal to 14, deposited on said surface of the semiconductor. According to a second aspect there is provided a fabrication method for forming a kagome lattice or other lattice structure such as a honeycomb or Moiré super lattice.

A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.

A seed layer for inducing nucleation to form a layer of material is described. In an embodiment, the seed layer comprising a layer of two-dimensional monolayer amorphous material having a disordered atomic structure adapted to create localised electronic states to form electric potential wells for bonding adatoms to a surface of the seed layer via van der Waals interaction to form the layer of material, wherein each of the electric potential wells has a potential energy larger in magnitude than surrounding thermal energy to capture adatoms on the surface of the seed layer. Embodiments in relation to a method for forming the seed layer, a heterostructure comprising the seed layer, a method for forming the heterostructure comprising the seed layer, a device comprising the heterostructure and a method of enhancing vdW interaction between adatoms and a surface of the seed layer are also described.

Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of In.sub.xGa.sub.1-xAs, In.sub.xGa.sub.1-xSb, In.sub.xGa.sub.1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.

A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

Information about a process for depositing at least one layer on a substrate in a process chamber is obtained via a method including the step of storing actuation data and sensor values as raw data in a log file, together with their time reference. Knowledge about the quality of the deposited layer is obtained by using the raw data. For this purpose, process parameters are obtained from the raw data by means of a computing apparatus. The beginning and the end of the process steps for processing the substrate and their respective types are identified by analyzing the time curve of the process parameters. For at least some of the process steps, characteristic process step quantities corresponding to the particular type of the process steps are calculated from the measured values, and the obtained process step quantities are compared with comparison quantities associated with one or more similar process steps.

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate; forming a conformal SiN, SiO.sub.xC.sub.yN.sub.z layer over side and bottom surfaces of the first trenches; filling the first trenches with SiO.sub.x; forming a first mask over portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate; removing exposed portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate, forming second trenches; forming III-V, III-V.sub.xM.sub.y, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V.sub.xM.sub.y, or Si nanowires and intervening first trenches; removing the SiO.sub.x layer, forming third trenches; and removing the second mask.