Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings.

The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer,

A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

The present application discloses a method for manufacturing a metal gate MOS transistor, comprising: step 1, forming metal gates; step 2, forming a first dielectric layer disposed on the metal gates and the zeroth interlayer film; step 3, forming an opening for the zeroth metal layer; step 4, forming a first Ti layer and a second TiN layer; and step 5, filling the opening of the zeroth metal layer with a metal material. After step 1 and before step 4, performing the first annealing at a first temperature to adjust a threshold voltage of the metal gate MOS transistor to a target value. After step 4 and before step 5, performing the second annealing at a second temperature lower than the first temperature to adjust on-resistance of the metal gate MOS transistor.

A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.

A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.