A manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region; forming first gate oxide layers in a non-gate region of the high-voltage device region and the low-voltage device region and a second gate oxide layer in a gate region of the high-voltage device region; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; forming a first polysilicon gate and a first sidewall structure on the surface of the first gate oxide layer of the low-voltage device region and a second polysilicon gate and a second sidewall structure on the surface of the second gate oxide layer; the width of the second gate oxide layer is greater than the width of the second polysilicon gate; performing source drain ions injection to form a source drain extraction region; after depositing a metal silicide area block (SAB), performing a photolithographic etching on the metal SAB and forming metal silicide. The above manufacturing method of a semiconductor device simplifies process steps and reduces process cost. The present invention also relates to a semiconductor device.

A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.

The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

A self-aligning preparation method for a drain underlap region in a tunnel field effect transistor: designing asymmetric side wall structures on two sides of the gate of a tunnel field effect transistor, the side of the gate closest to the source region being a thin side wall and the side of the gate closest to the drain region being a thick side wall; and using the source region thin side wall as a hard mask for implantation of the source region of the transistor and the drain region thick side wall as a hard mask for implantation of the drain region of the transistor. The present method effectively uses the thin side walls and thick side walls existing in standard CMOS processes to suppress the ambipolar effect of the tunnel field effect transistor without introducing special materials and special processes, and also optimizes the device variation characteristics. The present method ensures that the tunnel field effect transistor can be monolithically integrated with standard CMOS devices to implement more complex and diverse circuit functions.

An LDMOS device and a method for forming the LDMOS device are provided. The LDMOS device includes: a substrate formed with a source region, a drain region and a drift region; a gate structure; a silicide block layer; a first conductive structure having one end electrically connected with the source region, a second conductive structure having one end electrically connected with the drain region; a first metal interconnecting structure electrically connected with the other end of the first conductive structure, a second metal interconnecting structure electrically connected with the other end of the second conductive structure; a third conductive structure having one end disposed on a surface of the silicide block layer; and a third metal interconnecting structure electrically connected with the other end of the third conductive structure. The LDMOS device has increased breakdown voltage, and reduced on-resistance, and its preparation process is safer and easier to control.

In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

A memory device and a method for forming the same are provided. The method includes forming a plurality of gate structures on a substrate, forming a first spacer on opposite sides of the gate structures, filling a dielectric layer between adjacent first spacers, forming a metal silicide layer on the gate structures, conformally forming a spacer material layer over the metal silicide layer, the first spacer layer and the dielectric layer, and performing an etch back process on the spacer material layer to form a second spacer on opposite sides of the metal silicide layer.

A method for manufacturing a semiconductor structure is provided. The method comprises the following steps. A first silicon-containing gate electrode is formed on a semiconductor substrate in a first region. A second silicon-containing gate electrode is formed on the semiconductor substrate in a second region. A gate silicide element is formed on an upper surface of the first silicon-containing gate electrode. A source silicide element and a drain silicide element are formed on the semiconductor substrate on opposing sides of the second silicon-containing gate electrode respectively. The gate silicide element, the source silicide element and the drain silicide element are formed simultaneously.

A first source/drain (S/D) structure of a first transistor is formed on a substrate and positioned at a first end of a first channel structure of the first transistor. A first substitute silicide layer is deposited on a surface of the first S/D structure and made of a first dielectric. A second dielectric is formed to cover the first substitute silicide layer and the first S/D structure. A first interconnect opening is formed subsequently in the second dielectric to uncover the first substitute silicide layer. The first interconnect opening is filled with a first substitute interconnect layer, where the first substitute interconnect layer is made of a third dielectric. Further, a thermal processing of the substrate is executed. The first substitute interconnect layer and the first substitute silicide layer are removed. A first silicide layer is formed on the surfaces of the first S/D structure.

A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate, a gate electrode, a gate dielectric layer, first protection structures, a second protection structure and an insulating layer. The gate electrode is disposed within the substrate. The gate dielectric layer is disposed within the substrate and laterally surrounds the gate electrode. The first protection structures are disposed over the gate electrode. The second protection structure is disposed over the gate dielectric layer. The insulating layer is between the second protection structure and the gate dielectric layer.