A post driver includes an input pair circuit, a protection circuit, a common mode sensing circuit and an amplifier. The input pair circuit outputs a first signal through a first node and outputs a second signal through a second node according to a first input signal and a second input signal. The protection circuit provides the input pair circuit with voltage protection according to multiple first bias voltages and a second bias voltage, transmits the first signal to a first load to generate a first output signal, and transmits the second signal to a second load to generate a second output signal. The common mode sensing circuit senses a level of the first node and a level of the second node to generate a feedback signal. The amplifier generates the second bias voltage according to a reference signal and the feedback signal.

An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.

We describe an integrated circuit is disclosed which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.

An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

A differential output circuit includes: input transistors that receive differential input signals; n stages of cascode transistors (n2) cascode connected to the input transistors; output terminals connected to the drains of n-th stage cascode transistors; an intermediate potential generating circuit that supplies an intermediate potential of potentials of the output terminals to the gates of the n-th stage cascode transistors; and a dividing circuit that supplies divided potentials resulting from the intermediate potential being divided into (n1) stages to the respective gates of the (n1)-th through first stages of the cascode transistors in descending order of potential.

An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.

A differential output circuit includes: input transistors that receive differential input signals; n stages of cascode transistors (n2) cascode connected to the input transistors; output terminals connected to the drains of n-th stage cascode transistors; an intermediate potential generating circuit that supplies an intermediate potential of potentials of the output terminals to the gates of the n-th stage cascode transistors; and a dividing circuit that supplies divided potentials resulting from the intermediate potential being divided into (n1) stages to the respective gates of the (n1)-th through first stages of the cascode transistors in descending order of potential.

Provided are a differential amplifier forming a first feedback loop and a second feedback loop by including feedback loop circuits, an electronic device, and an operating method thereof. The differential amplifier configured to generate at least one pair of differential output signals by amplifying at least one pair of differential input signals and to generate an output common-mode signal based on the at least one pair of differential output signals. The main amplifier includes a first current mirror that generates first currents. A first feedback loop circuit is connected to an output node of the main amplifier which outputs the output common-mode signal, and forms a first feedback loop that feeds back the output common-mode signal. A second feedback loop circuit generates a control signal that controls the first currents based on the output common-mode signal, and forms a second feedback loop.

The present disclosure provides a neuromodulation device that comprises at least one amplifier circuit that suppresses a common mode (CM) voltage signal in the input voltage signal. The amplifier circuit comprises an input stage to receive the input voltage signal, and a differential transconductor to provide an output current signal based on a DM voltage signal in the input voltage signal. The transconductor is provides a first CM voltage signal tapped after a non-inverting input, and a second CM voltage signal tapped after am inverting input, to CM amplifier of the amplifier circuit. The CM amplifier combines the first CM voltage signal with the second CM voltage signal, amplifies the combined CM voltage signal with an inverting gain, and provides the inverted CM voltage signal back to the non-inverting input and the inverting input of the transconductor for enabling the CM suppression.