An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.

A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.

A sample-and-hold amplifier can include: an operational amplifier; a sampling capacitor having a first terminal coupled to an inverting input terminal of the operational amplifier, and a second terminal coupled to a reference ground; and a switching circuit configured to switch feedback paths of the sample-and-hold amplifier in a first stage and a second stage, such that an offset voltage of the operational amplifier is at least partially eliminated.

A balanced differential transimpedance amplifier with a single-ended input operational over a wide variation in the dynamic range of input signals. A threshold circuit is employed to either or a combination of (1) generate a varying decision threshold to ensure a proper slicing over a wide range of input current signal levels; and (2) generate a bias current and voltage applied to an input of a transimpedance stage to cancel out a dependence of the transimpedance stage voltage input on input current signal levels.

An operational amplifier comprises a front stage and an output stage. The front stage comprises a first input transistor, a second input transistor, a first node, a second node, and a first current mirror. A first voltage based on a first current through the first input transistor is generated on the first node. A second voltage based on a second current through the second input transistor is generated on the second node. The output stage is configured to output an output voltage based on at least one of the first voltage and the second voltage. The first current mirror comprises a first transistor having a drain connected to the first node, a second transistor having a drain connected to the second node, and a first offset canceling capacitor connected between gates of the first transistor and the second transistor.

A differential amplifier circuit generates a first current and a second current having a current difference obtained by amplifying a voltage difference between an input voltage and a reference voltage. An output stage supplies current proportional to the first current to an output node. A current conversion circuit discharges current proportional to the second current from the output node. After connecting the output node to a ground node in response to a reset signal, a latch circuit disconnects the output node from the ground node after reset cancellation. Thereafter, when voltage at the output node rises from the ground voltage in a case where a level relationship between the input voltage and the reference voltage is reversed from a reset cancellation time point, the latch circuit fixes the voltage at the output node to a power supply voltage by a positive feedback latch operation.

Disclosed herein is an operational amplifier including a non-inverting input terminal, an inverting input terminal, a P-type metal oxide semiconductor input differential pair, a first input tail current source, an N-type metal oxide semiconductor input differential pair, a second input tail current source, an output stage, a first correction circuit, and a second correction circuit. The first correction circuit and the second correction circuit operate over an operation region of the P-type metal oxide semiconductor input differential pair, an operation region of the N-type metal oxide semiconductor input differential pair, and a transition region in which both the P-type metal oxide semiconductor input differential pair and the N-type metal oxide semiconductor input differential pair operate.

A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.

A differential amplifier circuit generates a first current and a second current having a current difference obtained by amplifying a voltage difference between an input voltage and a reference voltage. An output stage supplies current proportional to the first current to an output node. A current conversion circuit discharges current proportional to the second current from the output node. After connecting the output node to a ground node in response to a reset signal, a latch circuit disconnects the output node from the ground node after reset cancellation. Thereafter, when voltage at the output node rises from the ground voltage in a case where a level relationship between the input voltage and the reference voltage is reversed from a reset cancellation time point, the latch circuit fixes the voltage at the output node to a power supply voltage by a positive feedback latch operation.