A DAC, for use in an iADC, is configured for converting a multi-bit word to an analog feedback signal. The DAC comprises a MMS logic block. It further comprises a plurality of output elements configured to generate respective analog portions based on a selection vector and a signal combiner for combining the analog portions to the analog feedback signal. In the MMS logic block switching blocks are arranged cascaded. Each switching block receives at least a portion of the multi-bit word, splits the portion into two sub-portions and forwards them to one subsequent switching block or to one output element. A weight factor is adjusted by multiplying it with the difference of the two sub-portions. A weight accumulator accumulates successive adjusted weight factors, wherein the way of splitting the portion of a further multi-bit word is determined based on the sign of the weight accumulator.

A dynamic element matching (DEM) encoder is provided that converts an N-bit digital codeword into a pattern of 1-bit values. The DEM encoder includes a binary switching tree that includes plurality of switching blocks interconnected between an encoder input and a plurality of encoder outputs. The plurality of switching blocks are configured to receive a plurality of first control signals such that each switching block receives a respective first control signal and is independently programmable based on the respective first control signal into a first mode or a second mode. Each switching block includes a splitting circuit programmed into the first mode or the second mode to split a digital input into two digital outputs using either both a first splitting operation and a second splitting operation that is different from the first splitting operation or the first splitting operation over the plurality of sampling intervals.

The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Radar frequency range signals (e.g., 1 to 100 gigahertz) are often generated by upconverting a reference frequency to a transmission frequency, and a received signal may be downconverted to analyze information encoded on the transmission via modulation. Modulation may be achieved via a fractional frequency divider in a phase-locked loop, but fractional spurs may reduce the signal-to-noise ratio. Additionally, the ramp slope may vary due to phase-locked loop momentum. Instead, a clock generator may generate clock signals for a digital front end comprising a digital signal modulator that generates modulated digital values comprising quadrature representations of a radar modulation signal, which are encoded by a radiofrequency digital-to-analog converter (RF-DAC). The RF-DAC analog signal may be upconverted to a radar frequency and transmitted. A receiver may receive, downconvert, and analyze a reflection of the radar transmission, e.g., to perform range detection based on a frequency ramp encoded by the radar transmission.

A sensor signal processing circuit including a delta-sigma analog-to-digital converter (ADC) and a control circuit is disclosed. The circuit is configured to adaptively activate one or more segments of current elements for sequential sampling periods based on a digital signal input to a DAC, wherein less than N current elements are allocated to each segment, each current element in an active segment is enabled and either contributes to a feedback signal of the DAC or does not contribute to the feedback signal, and current elements not in an active segment are disabled. The circuit can be integrated with an acoustic or other sensor as part of a sensor assembly.

The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Techniques for compensating high-speed digital-to-analog converters (DACs) for static mismatch are described. In ideal circumstances, the current sources of a DAC are identical to each other, leading to a frequency response presenting a relatively flat noise spectrum. In the presence of mismatch, however, the response creates unwanted spurious content, which can negatively affect the DAC's dynamic range. The techniques described herein involve randomized thermometric encoders. First, the direction in which a packet contracts or expands, depending on the value to be encoded, can be randomized. Second, pairs of values in a packet (and/or pairs of values outside the packet) can be swapped with one another in a randomized fashion. Third, the decision of whether to apply randomization or not can itself be randomized. By applying one or more of the randomization techniques described herein, the negative effects of switch timing offset and errors in DC linearity can be mitigated.

A signal processing circuit includes a filter generating a quantizer input signal from a noise shaping input signal and a quantizer output signal. A quantizer divides the quantizer input signal by a scaling factor to produce a noise shaping output signal and multiplies the noise shaping output signal by the scaling factor to produce the quantizer output signal. Receiver circuitry scales the quantizer output signal by a second scaling factor. A dynamic range optimization circuit compares a current value of the noise shaping input signal to a threshold value, lowers or raises the scaling factor in response to the comparison, and proportionally lowers or raises the scaling factor such that a ratio between the scaling factor and second scaling factor remains substantially constant.

A delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a near-zero asymmetric quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter such that the quantized output signal has a plurality of quantization levels, wherein the plurality of quantization levels are asymmetric to zero.

A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.