This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit receives an analogue input signal (S.sub.IN) and outputs a digital output signal (S.sub.OUT). The circuit has a sampling capacitor, a controlled oscillator and a counter for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor is coupled to an input node for the input signal, e.g. via switch. In the read-out phase, the sampling capacitor is coupled to the controlled oscillator, e.g. via switch, such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.

A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.

A biasing scheme for a voltage-to-time converter (VTC). An example biasing circuit generally includes a reference current source; a feedback loop current source; an amplifier having a first input coupled to a target voltage node, having a second input, and having an output coupled to a control input of the reference current source and to a control input of the feedback loop current source; a first capacitive element; a first switch coupled in parallel with the first capacitive element; a second switch coupled between the feedback loop current source and the first capacitive element; and a third switch coupled between the first capacitive element and the second input of the amplifier.

An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.

An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.

A successive approximation (SA) AD converter includes a SA control circuit generating a digital output signal based on an output from a comparator; a first capacitor coupled to an input of the comparator, receiving an analog input signal, and capable of storing electric charges; a second and a third capacitor groups coupling to a reference voltage and storing electric charges previously. The SA control circuit operates for each SA step that the second or the third capacitor group is coupled to a non-inverting input of the comparator and the other is coupled to an inverting input of the comparator based on the output from the comparator. The SA control circuit operates that capacitor terminals of the second and the third capacitor groups coupled to the input of the comparator have the same potential when the reference voltage is stored previously in the second and the third capacitor groups.

Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

A successive approximation (SA) AD converter includes a SA control circuit generating a digital output signal based on an output from a comparator; a first capacitor coupled to an input of the comparator, receiving an analog input signal, and capable of storing electric charges; a second and a third capacitor groups coupling to a reference voltage and storing electric charges previously. The SA control circuit operates for each SA step that the second or the third capacitor group is coupled to a non-inverting input of the comparator and the other is coupled to an inverting input of the comparator based on the output from the comparator. The SA control circuit operates that capacitor terminals of the second and the third capacitor groups coupled to the input of the comparator have the same potential when the reference voltage is stored previously in the second and the third capacitor groups.

A pseudo differential analog-to-digital converter includes: a first capacitor array and a second capacitor array respectively coupled to input terminals of an analog-to-digital circuit; where an output terminal of the first capacitor array receives a first reference voltage, and an output terminal of the second capacitor array receives a second reference voltage; and where a difference between the first and second reference voltages is set between zero and a peak value of an analog input signal.

A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) having a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and a second DAC having a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases.