An active element array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a first patterned conductive layer, a second metal layer, a second insulation layer, and a second patterned conductive layer is provided. The semiconductor layer is disposed on the first insulation layer. The first patterned conductive layer is disposed on the first insulation layer and covers a partial region of the semiconductor layer. The second metal layer is disposed on the first patterned conductive layer. The second insulation layer is disposed on the second metal layer and covers at least a partial region of the second metal layer, the first patterned conductive layer, the semiconductor layer, and the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer and overlapped with the first patterned conductive layer. A display panel is also provided.

An array substrate manufacturing method, an array substrate formed by the method, and a liquid crystal apparatus are disclosed. The method includes steps of depositing a first metal layer to form a plurality of scanning lines; depositing a first insulating layer and performing a patterning process on the first insulating layer; depositing a semiconductor layer and a second metal layer to form a plurality of data lines and thin-film transistors; depositing a second insulating layer to form a plurality of contact holes; and depositing a transparent layer to form a plurality of pixel electrodes.

A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

The present invention provides a manufacture method of a TFT array substrate and a TFT array substrate structure, and the TFT array substrate structure comprises a substrate (1), a first metal electrode (2) on the substrate (1), a gate isolation layer (3) positioned on the substrate (1) and completely covering the first metal electrode (2), an island shaped semiconductor layer (4) on the gate isolation layer (3), a second metal electrode (6) on the gate isolation layer (3) and the island shaped semiconductor layer (4), a protecting layer (8) on the second metal electrode (6), a color resist layer (7) on the protecting layer (8), a protecting layer (12) on the color resist layer (7) and a first pixel electrode layer (9) on the protecting layer (12); a via (81) is formed on the protecting layer (8), the color resist layer (7) and the protecting layer (12), and an organic material layer (10) fills the inside of the via (81).

A method for fabricating a stacked thin film transistor (TFT) structure comprises: forming at least two TFTs on a substrate of a display device; at least partially covering the at least two TFTs with an insulating layer; forming a common electrode on the insulating layer and the at least two TFTs; covering, at least partially, the common electrode with a dielectric material, wherein the insulating layer, the common electrode, and the dielectric material each include a contact hole; filling, at least partially, the contact hole with a conductive material; and depositing the conductive material over the dielectric material to form a pixel electrode.

The present disclosure provides an array substrate, a method of manufacturing the same, a display panel and a display device. The array substrate comprises a plurality of gate lines and a plurality of data lines arranged to cross with each other and define a plurality of pixel areas, each of the pixel areas comprising a thin film transistor. The array substrate further comprises a first insulating layer arranged above the thin film transistors and the data lines; a metal layer arranged above the first insulating layer; a second insulating layer arranged above the metal layer; and a pixel electrode and a common electrode arranged above the second insulating layer, between which a third insulating layer is provided. The common electrode in each of the pixel areas at least comprises two slits and the metal layer overlies the data lines.

An active matrix substrate for a liquid crystal panel of an FFS mode includes gate lines, data lines, pixel circuits each including a switching element and a pixel electrode, a protective insulating film formed in a layer over these elements, and a common electrode 30 formed in a layer over the protective insulating film. The common electrode 30 has slits 31 corresponding to the pixel electrode, for generating a lateral electric field to be applied to a liquid crystal layer. In the common electrode 30, a cutout above data line 32 having a portion extending in the same direction as that of the data line is formed in a region including a part of a placement region for the data line. On a counter substrate, a black matrix is formed in a position that faces a region including placement regions for the gate line, the data line, the switching element, and the cutout above data line 32. This reduces display failure caused by a load of the data line.

A thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. The semiconductor layer overlaps the gate electrode and includes a channel layer comprising an oxide semiconductor and an auxiliary layer comprising amorphous silicon. The source electrode and the drain electrode are separated from each other and connected to the semiconductor layer. A thin film transistor array panel and method of manufacturing same also is disclosed.

The present disclosure provides an array substrate, a display panel, a display device and a method for manufacturing the array substrate. The array substrate includes: a plurality of gate lines and a plurality of data lines arranged in a crisscross manner on a base substrate, so as to define a plurality of subpixels; and a common electrode arranged opposite to each of the plurality of subpixels. At least one of the subpixels is provided with a common electrode line connected to the common electrode at an identical subpixel region.

Embodiments of the present disclosure provide an array substrate and a display device. The array substrate includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines crossing one another to bound pixel units and the pixel unites each including a pixel electrode and a thin film transistor, which includes a drain electrode, the array substrate further includes a common electrode line, the drain electrode includes an extension portion and the common electrode line and the extension portion form a light blocking structure together such that an orthographic projection of the light blocking structure on a plane where the pixel electrode is located is located near an edge of the pixel electrode. The array substrate provided by the present disclosure is applied to a display device.